Publication Release Date: August 2006 - 47 - Revision 1.0 Bit 4: Transmitter Busy (XMIT_BUSY) When high, the " />
參數(shù)資料
型號(hào)： W83L951DG
廠商： Nuvoton Technology Corporation of America
文件頁(yè)數(shù)： 60/112頁(yè)
文件大?。?/td> 0K
描述： IC EMBEDDED CNTRLR 128-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： W83
核心處理器： 8051
芯體尺寸： 8-位
速度： 24MHz
連通性： 主機(jī)接口，PS/2，SMBus，UART/USART
外圍設(shè)備： PWM，WDT
輸入/輸出數(shù)： 104
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b; D/A 2x8b
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 128-LQFP
包裝： 托盤
W83L951DG/W83L951FG
Publication Release Date: August 2006
- 47 -
Revision 1.0
Bit 4: Transmitter Busy (XMIT_BUSY)
When high, the XMIT_BUSY bit is a status bit indicating that the PS2 channel is actively transmitting
data to the PS2 peripheral device. Writing to the Transmit Register whether the channel ready to
transmit will cause the XMIT_BUSY bit to assert and remain asserted until one of the following
conditions occur and an Interrupt is generated..
The falling edge of the 11th CLK; upon a Transmit Timeout condition (XMIT_TIMEOUT goes high);
Upon the PS2_T/R bit being written to 0.
Upon the PS2_EN bit being written to 0.
Note: An interrupt is generated on the high to low transition of XMIT_BUSY.
Bit 3: Framing Error (FE)
When receiving data the stop bit is clocked in on the falling edge of the 11th CLK edge. If the channel
has been set to expect either a high or low stop bit and the 11th bit is contrary to the expected stop
polarity, then the FE and REC_TIMEOUT bits are set following the falling edge of the 11th CLK edge
and an Interrupt is generated. Writing high will clear this bit.
Bit 2: Parity Error (PE)
When receiving data the parity bit is clocked in on the falling edge of the 10th CLK edge. If the channel
has been set to expect either even or odd parity and the 10th bit is contrary to the expected parity,
then the PE and REC_TIMEOUT bits are set following the falling edge of the 10th CLK edge and an
Interrupt is generated. Writing high will clear this bit.
Bit 1: Receiver Timeout (REC_TIMEOUT)
Under PS2 automatic operation, PS2_EN=1, this bit is set on one of 4 receive error conditions, and in
addition the Channel’s CLK line is automatically pulled low and held for a period of 300us following
assertion of the REC_TIMEOUT bit:
When the receiver bit time (time between falling edges) exceeds 300us(Input clock=24MHz) or
600us(Input clock=12MHz).
If the time from the 1st (start, falling edge) bit to the 10th (stop, falling edge) bit exceeds 2ms.
On a receive parity error along with the parity error (PE) bit.
On a receive framing error due to an incorrect STOP bit along with the framing error (FE) bit. Writing
high will clear this bit.
Note: An Interrupt is generated on the low to high transition of the REC_TIMEOUT bit.
Bit 0: Data Ready (RDATA_RDY)
Receive Data Ready: Under normal operating conditions, this bit is set following the falling edge of the
11th clock given successful reception of a data byte from the PS/2 peripheral (i.e., no parity, framing,
or receive timeout errors) and indicates that the received data byte is available to be read from the
Receive Register. This bit may also be set in the event that the PS2_EN bit is cleared following the
10th CLK edge (see the PS2_EN bit description for further details). Writing high will clear this bit.
Note: An Interrupt is generated on the low to high transition of the RDATA_RDY bit.
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