
W921E400A/W921C400
Publication Release Date: July 1999
- 11 -
Revision A3
Special Control Register Map, continued
ADDR.
DESCRIPTION
ABBREVIATION
INITIAL VALUE
029H
Reserved
-
02AH
TM2 Control Register
(TM2CR)
00H
02BH
TM2 MSB Data Register
(TM2MSB)
0FH
02CH
TM2 LSB Data Register
(TM2LSB)
0FH
02DH
TM2 Status Register
(STTM2)
00H
02EH
TM2 Trigger Condition Register
(TGTM2)
00H
02FH
TM3 Control Register
(TM3CR)
00H
030H
TM3 MSB Data Register
(TM3MSB)
0FH
031H
TM3 LSB Data Register
(TM3LSB)
0FH
032H
TM3 Status Register
(STTM3)
00H
033H
Reserved
-
034H
Interrupt Enable Flag
(ENINT)
00H
035H
Stop Mode Released Flag
(STPRF)
08H
036H
Hold Mode Released Flag 1
(HMRF1)
00H
037H
Hold Mode Released Flag 2
(HMRF2)
00H
038H
Hold Mode Released Flag 3
(HMRF3)
00H
039H
Interrupt Control Register 1
(INTCT1)
00H
03AH
Interrupt Control Register 2
(INTCT2)
00H
03BH
Interrupt Control Register 3
(INTCT3)
00H
03CH
Hold Released Status Flag 1
(HRSTS1)
00H
03DH
Hold Released Status Flag 2
(HRSTS2)
00H
03EH
Hold Released Status Flag 3
(HRSTS3)
00H
03FH
Beep Tone Generator Register
(BTGR)
00H
6.2.2 Stack Register Area
There is one 8-bit stack pointer in this chip, and the stacks located address are 040H to 0FFH. After
power on reset the stack pointer will be set to 0FFH. The stack pointer will be decreased by 4 when
the CALL/CALLP or interrupt is accepted, and will be increased by 4 when the RTN or RTNI
instruction is executed. The format of the stack content is shown in the following table.