參數(shù)資料
型號(hào)： W921C400
英文描述： Microcontroller
中文描述： 微控制器
文件頁(yè)數(shù)： 13/53頁(yè)
文件大小： 394K
代理商： W921C400
W921E400A/W921C400
Publication Release Date: July 1999
- 13 -
Revision A3
The W921E400A/W921C400 provides a crystal or RC oscillation circuit selected by bit0 of INI
register (refer to section 6.14) to generate the system clock through external connections. If a crystal
oscillator is used, a crystal or ceramic resonator must be connected to OSCI and OSCO, and the
capacitor must be connected if an accurate frequency is needed. The oscillator configuration is shown
as follows.
OSCI
OSCO
or
OSCI
OSCO
RC type
Crystal Type
6.4 Initial State
The W921E400A/W921C400 is reset either by a power-on reset or by using the external RESET pin.
The initial state of the W921E400A/W921C400 after the reset function is executed is described
below. The EVF interrupt request signal register value is random, so user must do CLR
EVF,#11111111b instruction to clear all interrupt request signals after power-on reset.
Program counter (PC)
Stack pointer
Special function registers
TM0, TM2, TM3 input clock
TM0, TM2, TM3 contents
I/O port
PM registers
DTMF output
EVF interrupt request signal register
0000H
0FFH
Refer to section 6.2.1
Fosc / 8
0FFH
Input mode
1111B
Disable (H-Z)
Random
6.5 Input/Output
There are 21 I/O pins. All the I/O pins will remain in the input mode after power on reset.
The I/O instructions are described as follows:
MOV
MOV
MOV
MOV
A, Px
B, Px
Px, A
Px, B
Input port x to A accumulator
Input port x to B accumulator
Output A accumulator data to port x.
Output B accumulator data to port x.
The input or output status of port 2 to port 6 can be pin controlled by port mode register (PMx, where
x = 2 to 6). Data 0 in PMx indicates the corresponding pin as output mode, and data 1 indicates the
relative pin as input mode. For example, MOV PM3, #0101B, it sets P3.0 and P3.2 in input mode and
P3.1 and P3.3 in output mode. The I/O instructions don't affect the input or output mode in port2 to
port6.
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