參數(shù)資料
型號： W921C840
英文描述： Microcontroller
中文描述： 微控制器
文件頁數(shù)： 31/53頁
文件大?。?/td> 394K
代理商： W921C840
W921E400A/W921C400
Publication Release Date: July 1999
- 31 -
Revision A3
6.11.2 Interrupt Enable Flag
When the interrupt is enabled by the event, the program counter will jump to the interrupt address and
the enable interrupt flag (ENINT) bit0 is cleared, at the same time, all the interrupt will be disabled.
The only way to enable the interrupt again is to set the ENINT bit0 or execute the RTNI instruction.
ENINT register: (address = 034H, default data = 0H)
b3
b2
b1
b0
0: Disable all interrupt
1: Enable all interrupt
Reserved
Reserved
Reserved
When the interrupt is enabled by the event, the individual interrupt request signal is cleared by the
hardware automatically but the other interrupt request signals will remain the same condition. The
only method of resetting the interrupt request signal is to execute the instruction CLR EVF, #I (I is a
8bits data, for example, CLR EVF, #00000001b instruction implies to clear TM0 interrupt request
signal), it is a 2 words / 2 cycles instruction; the format of the immediate data is shown below.
i3
i2
i1
i0
1: TM2 interrupt request signal is cleared
1: TM0 interrupt request signal is cleared
1: TM3 interrupt request signal is cleared
i4
i5
i6
i7
1: Serial port interrupt request signal is cleared
1: P4.2 interrupt request signal is cleared
1: INT0 pin interrupt request signal is cleared
1: Comparator interrupt request signal is cleared
Reserved
6.12 Operating Mode
There are three types of operating mode in this chip
normal mode, hold mode and stop mode.
6.12.1 Normal Mode:
All functions works well and the
μ
C operates according to the clock generated by the system clock.
6.12.2 Hold Mode:
In hold mode, all operations of
μ
C cease, except for the operation of the oscillator, timer/counter,
serial port and interrupt active pins. The
μ
C enters hold mode when the HOLD instruction is executed.
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