參數(shù)資料
型號: W925E625
英文描述: Telephone Controller
中文描述: 電話控制器
文件頁數(shù): 18/71頁
文件大小: 1055K
代理商: W925E625
W925E/C625
8-bit CID Microcontroller
PORT 1
Revision : A6
-18-
Release Date : 2002/7/2
(initial=FFh, input mode)
2
1
P1.2
P1.1
Bit:
7
6
5
4
3
0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.0
Mnemonic: P1
Address: 90h
P1.7-0: P1 can be selected as input or output mode by the P1IO register , At initial reset , P1IO is
set to 1, so P1 is used as input mode . When P1IO is set to 0 , the P1 is used as
CMOS output mode . When P1EF are set and P1IO are set as input mode , P1 can be
used as external interrupt source. The functions are listed below .
P1.0 : INT2.0
P1.1 : INT2.1
P1.2 : INT2.2
P1.3 : INT2.3
P1.4 : INT3.0
P1.5 : INT3.1 External Interrupt 3
P1.6 : INT3.2
External Interrupt 3
P1.7 : INT3.3
External Interrupt 3
External Interrupt 2
External Interrupt 2
External Interrupt 2
External Interrupt 2
External Interrupt 3
EXTERNAL INTERRUPT FLAG
(initial=00H)
Bit:
7
-
6
-
5
-
4
3
2
1
0
COMPF
DIVF
CIDF
IE3
IE2
Mnemonic: EXIF
Address: 91h
COMPF: Comparator flag. Set by hardware when RESC bit is from low to high.
DIVF: Divider overflow flag.
CIDF: CID interrupt flag. Set by hardware when at least one of CID flags is set.
IE3:
External Interrupt 3 flag. Set by hardware when a falling edge is detected on INT3.
IE2:
External Interrupt 2 flag. Set by hardware when a falling edge is detected on INT2.
P1 PINS STATUS
(initial=00H)
Bit:
7
6
5
4
3
2
1
0
P1.7SR P1.6SR P1.5SR P1.4SR P1.3SR P1.2SR P1.1SR P1.0SR
Mnemonic: P1SR
Address: 93h
P1SR: Set when a falling edge is detected on the corresponding P1 pin, clear by software.
P0 I/O PORT CONTROL
(initial=FFH)
Bit:
7
6
5
4
3
2
1
0
P0.7IO P0.6IO P0.5IO P0.4IO P0.3IO P0.2IO P0.1IO P0.0IO
Mnemonic: P0IO
Address: 94h
P0IO: P0 pins I/O control.
1: input mode
0: output mode
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