
W9451GBDA-6
Publication Release Date: March 15, 2002
- 3 -
Revision A1
5. PIN DESCRIPTIONS
PIN
NAME
FUNCTION DESCRIPTION
CLKn, CLKn
Clock Input
CLKn and CLKn are differential clock inputs. All input command
signals are sampled at the positive edge of CLK(except for DQ, DM
and CKE).
CSn
Chip select
Disable or enable the command decoder. When command decoder is
disabled, new command is ignored and previous operation continues.
CKEn
Clock Enable
CKE controls the clock activation and deactivation. When CKE is low,
Power Down mode, Suspend mode, or Self-Refresh mode is entered.
A0
A12
Address
Multiplexed pins for row and column address.
Row address: A0
A12. Column address: A0
A9.
BA0
BA1
Bank Select
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row Address
Strobe
Command input. When sampled at the rising edge of the clock, RAS ,
CAS and WE define the operation to be executed.
CAS
Column
Address Strobe
Referred to RAS
WE
Write Enable
Referred to RAS
DM0
DM7
Input/Output
Mask
The output buffer is placed at Hi-Z when DM is sampled high in read
cycle. In write cycle, sampling DM high will block the write data.
DQ0
DQ63
Data
Input/Output
Multiplexed pins for data output and input
DQS0
DQS7
Data Strobe
Input/Output
Output with read data, input with write data. DQS is edge-aligned with
read data, centered in write data.
V
DD
Power (+2.5V)
Power supply (2.5V).
V
SS
Ground
Ground
V
REF
Reference
Voltage
SSTL-2 Reference voltage
V
DDSPD
SPD Power
Separated power supply for SPD EEPROM (2.3V
3.6V)
SCL
Serial Clock
Clock for serial presence detection
SDA
Serial Data I/O
Data line for serial presence detection
SAn
SPD Address
Line
System assigned address (SA0
SA2) to identify different memory
module in a system board.
NC
No Connection
No connection