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參數(shù)資料
| 型號： | W9451GBDA-6 |
| 英文描述： | SDRAM|DDR|64MX64|CMOS|DIMM|184PIN|PLASTIC |
| 中文描述： | 內(nèi)存|復(fù)員| 64MX64 |的CMOS |內(nèi)存| 184PIN |塑料 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 284K |
| 代理商： | W9451GBDA-6 |
W9451GBDA-6
Publication Release Date: March 15, 2002
- 9 -
Revision A1
(8)
V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set
equal to V
REF
and must track variations in the DC level of V
REF
.
These parameters depend on the output loading. Specified values are obtained with the output open.
(10) Transition times are measured between V
IH
min.(AC)
and V
IL
max.(AC)
.Transition (rise and fall) of input signals have a
fixed slope.
(11) If the result of nominal calculation with regard to t
CK
contains more than one decimal place, the result is rounded up to
the nearest decimal place. i.e., t
DQSS
= 0.75
×
t
CK
, t
CK
= 7.5 nS, 0.75
×
7.5 nS = 5.625 nS is rounded up to 5.6 nS.
(12) V
X
is the differential clock cross point voltage where input timing measurement is referenced.
(13) V
ID
is magnitude of the difference between CLK input level and
CLK
input level.
(14) V
ISO
means {V
ICK
(CLK) + V
ICK
(
CLK
)}/2.
(15) Refer to the figure below.
(16) t
AC
and t
DQSCK
depend on the clock jitter. These timing are measured at stable clock.
(9)
CLK
CLK
V
SS
V
ICK
V
X
V
X
V
X
V
X
V
X
V
ICK
V
ICK
V
ICK
V
ID(AC)
V
ID(AC)
0 V Differential
V
ISO
V
ISO(min)
V
ISO(max)
V
SS
(17) t
AC
and t
DQSCK
depend on the clock jitter. These timing are measured at stable clock.
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