參數(shù)資料
型號(hào)： W9966CF
文件頁(yè)數(shù)： 18/44頁(yè)
文件大?。?/td> 278K
代理商： W9966CF
Prel i m nary -18- November 1997
W9966CF/TF
Video Camera Interface Controller with Compression
D7
D6
D5
D4
D3
D2
D1
D0
1
R#/W
Index
Bit 7
Always 1, required for ECP
Bit 6
Read#/Write Select for All Subsequent Data Cycles
0 = Read
1 = Write
Bits 4-0
Index
An 5-bit value determines which 8-bit register will be
accessed for the subsequent data cycles.
Type
Bit 5
Type of Data Transfer
0 = Control register access
1 = CCD data transfer
FIGURE 7.3 PARALLEL PORT ADDRESS REGISTER DEFINITION
7.3.4Control Register Data Write
The desired control register data write operation is performed by :
1. using an address write cycle with data bits 7-5 = 110, and bits 4-0 = index of the desired
register.
2. Write data to the desired register by performing a data write cycle.
7.3.5Control Register Data Read
The desired control register data read operation is performed by :
1. using an address write cycle with data bits 7-5 = 100, and bits 4-0 = index of the desired
register.
2. The W9966CF/TF performs an reverse data transfer phase for the desired register data
transfer.
7.3.6CCD Data Transfer (Peripheral to Host Only)
The CCD data transfer is performed by :
1. using an address write cycle with data bits 7-5 = 101, and bits 4-0 = XXXXX.
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