參數(shù)資料
型號(hào)： WARP20
廠商： 意法半導(dǎo)體
英文描述： 8-BIT FUZZY CO-PROCESSOR
中文描述： 8位模糊協(xié)處理器
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 275K
代理商： WARP20
ON-LINE MODE
In On-line mode (see figure 7) W.A.R.P.2.0 is en-
abled to elaborate input values and calculate out-
puts according to the fuzzy rules stored into the
microprogram. W.A.R.P.2.0reads the inputvalues
one a time in the input data bus using the
RD/READY signals. If the processor is workingin
SLAVE mode (see register bench description in
table5) the userhas toprovide the inputswith their
identificationnumbers(bymeansofSIS0-SIS2),so
it is possible to provide inputs in any order. In
SLAVE mode it is also possible to force
W.A.R.P.2.0 to start the elaboration phase (by
means of LASTIN) without providing all inputs, for
instancewheninputvariables changewithdifferent
speed. In this case the outputs that have not be
provided in this cycle,but sampled in the previous
ones, are recoveredfrom the internalbuffers.
When all inputs are given or a LASTIN signal is
given, the elaboration phase starts. The elabora-
tion phase is divided in twomain parts. During the
first one the input values are read and the corre-
spondingALPHAvalues (activation levels) are cal-
culated. In thesecond part the computationof the
fuzzy rules and the defuzzification are imple-
mented.
W.A.R.P.2.0 acquires each input in 8 clock pulses
(min). Sincethe acquisition phase isperformedby
the user by means of the handshakingsignals, 8
clock pulses per input are referred to the most
efficient case. In figure 6 are shown the perform-
0
64
128
192
256
0
2.000
4.000
6.000
8.000
Number of Rule s
Numbe r of Clock Pulse s
Number ofInputs = 8
Figure6. W.A.R.P.2.0performances
ances in case of 8 inputs. If you are using less
inputs youhave to subtract 8clock pulsesfor each
of them. The elaboration time for rule requires 32
clockpulses.
For instance if W.A.R.P.2.0 is working at a fre-
quency of 40 MHz (25ns period)with 8 inputs and
128 rules globally(forall outputs)the timerequired
to provideall outputs is 4000clkp*25ns= 100
μ
s.
On-line Phase Master
(”MASTER”set in the register bench)
On-line Phase Enable
OFL=LOW
Inputs Acquisition with
Handshaking Signals
(RD/READY)
CHIP PRESET
End of Acquisition Phase
Start Elaboration Pha se
Elaboration Phase
Outputs Gen eration
DS=HIGH
On-line Pha se Slave
(”SLAVE” set in the register bench)
On-line Phase Enable
OFL=LOW
Acquisition with
Handshaking by
specifying which inputs
is on the input bus by
means of SIS0-SIS2
CHIP PRESET
End of Acquisition Phase
Start Elaboration Pha se
Elaboration Phase
Outputs Generation
DS=HIGH
Last Input has been
given
LASTIN=HIGH
Figure7. On-Linephase
7/28
W.A.R.P.2.0
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