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參數(shù)資料
| 型號： | WE32K32N-80H1CA |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 32K X 32 EEPROM 5V MODULE, 80 ns, CPGA66 |
| 封裝： | 1.075 X 1.075 INCH, HERMETIC SEALED, CERAMIC, HIP-66 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 533K |
| 代理商： | WE32K32N-80H1CA |
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WE32K32-XXX
March 2006
Rev. 4
White Electronic Designs Corp. reserves the right to change products or specications without notice.
AC Read Characteristics (See Figure 6)
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
READ CYCLE
Symbol
-80
-90
-120
-150
Unit
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
80
90
120
150
ns
Address Access Time
tACC
80
90
120
150
ns
CS Access Time
tACS
80
90
120
150
ns
Output Hold from Add. Change, OE# or CS#
tOH
0000
ns
Output Enable to Output Valid
tOE
40
50
85
ns
Chip Select or OE# to Output in High Z
tDF
40
50
70
ns
READ
The WE32K32-XXX stores data at the memory location
determined by the address pins. When CS# and OE#
are low and WE# is high, this data is present on the
outputs. When CS# and OE# are high, the outputs are in
a high impedance state. This 2 line control prevents bus
contention.
FIGURE 6 – READ WAVEFORMS
NOTES:
1. OE# may be delayed up to tACS - tOE after the falling edge of CS# without impact on tOE or by tACC - tOE after
an address change without impact on tACC.
2. tCHZ, tOHZ are specied from OE# or CS# whichever occurs rst (CL = 5pF).
3. All I/O transitions are measured ±200 mV from steady state with loading as specied in "Load Test Circuits."
t
ADDRESS
CS#
OE#
OUTPUT
OH
tDF
tACC
t RC
tOE
tACS
OUTPUT
VALID
ADDRESS VALID
HIGH Z
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| WE32K32N-80H1I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
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