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參數(shù)資料
| 型號(hào)： | WED2ZL361MSJ35BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | SRAM |
| 英文描述： | 1M X 36 MULTI DEVICE SRAM MODULE, 3.5 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 0K |
| 代理商： | WED2ZL361MSJ35BC |
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
WED2ZL361MSJ
White Electronic Designs
CEx ADV WE BWx OE
CKE CLK Address Accessed
Operation
H
L
XXX
L
á
N/A
Deselect
X
H
XXX
L
á
N/A
Continue Deselect
LL
H
X
LL
á
External Address
Begin Burst Read Cycle
XHX
X
L
á
Next Address
Continue Burst Read Cycle
LL
H
X
H
L
á
External Address
NOP/Dummy Read
XHX
X
H
L
á
Next Address
Dummy Read
LLLL
X
L
á
External Address
Begin Burst Write Cycle
X
H
XL
á
Next Address
Continue Burst Write Cycle
LLL
H
X
L
á
N/A
NOP/Write Abort
XHXHX
L
á
Next Address
Write Abort
XXXXX
H
á
Current Address
Ignore Clock
NOTES:
1.
X means “Don’t Care.”
2.
The rising edge of clock is symbolized by (
á )
3.
A continue deselect cycle can only be entered if a deselect cycle is executed first.
4.
WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5.
Operation finally depends on status of asynchronous input pins (ZZ and OE).
6.
CEx refers to the combination of CE1, CE2 and CE2.
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
WRITE TRUTH TABLE
WE
BWa
BWb
BWc
BWd
Operation
H
XXXX
Read
L
H
Write Byte a
L
H
L
H
Write Byte b
L
H
L
H
Write Byte c
L
H
L
Write Byte d
LLLLL
Write All Bytes
L
HHHH
Write Abort/NOP
NOTES:
1.
X means “Don’t Care.”
2.
All inputs in this table must meet setup and hold time around the rising edge of CLK (
á).
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| WED2ZL361MSJ-BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NBL SSRAM MCP |
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