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參數(shù)資料
| 型號(hào)： | WED9LC6416V1312BI |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA153 |
| 封裝： | MO-163, BGA-153 |
| 文件頁數(shù)： | 26/27頁 |
| 文件大?。?/td> | 334K |
| 代理商： | WED9LC6416V1312BI |
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White Electronic Designs Corporation Westborough, MA (508) 366-5151
White Electronic Designs
WED9LC6416V
SDRAM AC CHARACTERISTICS
(VCC = 3.3V -5%/+10% UNLESS OTHERWISE NOTED)
Symbol
125MHz
100MHz
83MHz
Parameter
Min
Max
Min
Max
Min
Max
Units
Clock Cycle Time1
CL = 3
tCC
8
1000
10
1000
12
1000
ns
CL = 2
tCC
10
1000
12
1000
15
1000
Clock to valid Output delay1,2
tSAC
67
8
ns
Output Data Hold Time2
tOH
33
3
ns
Clock HIGH Pulse Width3
tCH
33
3
ns
Clock LOW Pulse Width3
tCL
33
3
ns
Input Setup Time3
tSS
2
ns
Input Hold Time3
tSH
11
1
ns
CLK to Output Low-Z2
tSLZ
22
2
ns
CLK to Output High-Z
tSHZ
77
8
ns
Row Active to Row Active Delay4
tRRD
20
24
ns
RAS\to CAS\Delay4
tRCD
20
24
ns
Row Precharge Time4
tRP
20
24
ns
Row Active Time4
tRAS
50
10,000
50
10,000
60
10,000
ns
Row Cycle Time - Operation4
tRC
70
80
90
ns
Row Cycle Time - Auto Refresh4,8
tRFC
70
80
90
ns
Last Data in to New Column Address Delay5
tCDL
11
1
CLK
Last Data in to Row Precharge5
tRDL
11
1
CLK
Last Data in to Burst Stop5
tBDL
11
1
CLK
Column Address to Column Address Delay6
tCCD
1.5
CLK
Number of Valid Output Data7
22
2
12
1
ea
NOTES:
1. Parameters depend on programmed CAS latency.
2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter.
3. Assumed input rise and fall time = 1ns. If tRISE or tFALL are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter.
4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the
next higher integer.
5. Minimum delay is required to complete write.
6. All devices allow every cycle column address changes.
7. In case of row precharge interrupt, auto precharge and read burst stop.
8. A new command may be given tRFC after self-refresh exit.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WED9LC6416V1510BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 SSRAM/4Mx32 SDRAM |
| WED9LC6416V1510BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 SSRAM/4Mx32 SDRAM |
| WED9LC6416V1512BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 SSRAM/4Mx32 SDRAM |
| WED9LC6416V1512BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 SSRAM/4Mx32 SDRAM |
| WED9LC6416V1610BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128Kx32 SSRAM/4Mx32 SDRAM |
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