參數(shù)資料
型號(hào)： WED9LC6416V1312BI
廠商： MICROSEMI CORP-PMG MICROELECTRONICS
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA153
封裝： MO-163, BGA-153
文件頁數(shù)： 27/27頁
文件大?。?/td> 334K
代理商： WED9LC6416V1312BI
9
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
WED9LC6416V
CLOCK FREQUENCY AND LATENCY PARAMETERS -125MHZ SDRAM
(UNIT =NUMBER OF CLOCK)
Frequency
CAS
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
Latency
70ns
50ns
20ns
10ns
125MHz (8.0ns)
3
9
6
3
2
3
1
100MHz (10.0ns)
3
7
5
2
1
83MHz (12.0ns)
2
6
4
2
1
CLOCK FREQUENCY AND LATENCY PARAMETERS -100MHZ SDRAM
(UNIT =NUMBER OF CLOCK)
Frequency
CAS
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
Latency
70ns
50ns
20ns
10ns
100MHz (12.0ns)
3
7
5
2
1
83MHz (12.0ns)
2
6
5
2
1
REFRESH CYCLE PARAMETERS
-10
-12
Parameter
Symbol
Min
Max
Min
Max
Units
Refresh Period1,2
tREF
—64
—
64
ms
NOTES:
1. 4096 cycles
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device.
SDRAM COMMAND TRUTH TABLE
SDCE
SDRAS
SDCAS
SDWE
BWE
A12,A13
SDA10
Notes
Function
A11-0
Mode Register Set
L
X
OP CODE
Auto Refresh (CBR)
L
H
X
Precharge
Single Bank
L
H
L
X
BA
L
2
Precharge all Banks
L
H
L
X
H
Bank Activate
L
H
X
BA
Row Address
2
Write
L
H
L
X
BA
L
2
Write with Auto Precharge
L
L
X
BA
H
2
Read
L
H
L
X
BA
L
2
Read with Auto Precharge
L
H
L
H
X
BA
H
2
Burst Termination
L
H
L
X
3
No Operation
L
H
X
Device Deselect
H
X
Data Write/Output Disable
X
L
X
4
Data Mask/Output Disable
X
H
X
4
NOTES:
1. All of the SDRAM operations are defined by states of SDCE, SDWE, SDRAS, SDCAS, and BWE
0-3 at the positive rising edge of the clock.
2. Bank Select (BA), A
12 (BA0)and A13 (BA ) select different banks.
3. During a Burst Write cycle there is a zero clock delay,for a Burst Read cycle the delay is equal to the CAS latency.
4. The BWE has two functions for the data DQ Read and Write operations. During a Read cycle,when BWE goes high at a clock timing the data outputs are disabled
and become high impedance after a two clock delay. BWE also provides a data mask function for Write cycles. When it activates,the Write operation at the clock
is prohibited (zero clock latency).
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