
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPY 256K 72V-X BX
Description
Symbol
Conditions
Min
Max
Units
Notes
Input High (Logic 1)Voltage
V
IH
Inputs
1.7
V
DD
+ 0.3
V
1
V
IHQ
Data (DQ)
1.7
V
DDQ
+ 0.3
V
1
Input Low (Logic 0) Voltage
V
IL
-0.3
0.7
V
1
Input Leakage Current
I
LI
0V
≤
V
IN
≤
V
DD
-2.0
2.0
μA
2
Ouptut Leakage Current
I
LO
Outputs disabled, 0V
≤
V
IN
≤
V
DDQ
(DQ
X
)
I
OH
= -1.0mA
-1.0
1.0
μA
Output High Voltage
V
OH
2.0
—
V
1
Output Low Voltage
V
OL
I
OL
= 1.0mA
—
0.4
V
1
Supply Voltage
V
DD
3.135
3.6
V
1
Output Buffer Supply
V
DDQ
2.375
2.9
V
1
Description
Control Input Capacitance
Common Control Input Capacitance (2)
Input/Output Capacitance (DQ)
Address Capacitance (SA)
Clock Capacitance (CLK)
Symbol
C
I
C
IC
C
O
Cs
A
C
CK
Max
6
15
10
15
12
Units
pF
pF
pF
pF
pF
Notes
1
1
1
1
1
BGA C
APACITANCE
(T
A
= +25°C, F = 1MH
Z
)
DC C
HARACTERISTICS
-55°C
≤
TA
≤
+125°C
E
LECTRICAL
C
HARACTERISTICS
A
ND
O
PERATING
CONDITIONS
-55°C
≤
TA
≤
+125°C
A
BSOLUTE
M
AXIMUM
R
ATINGS
*
Voltage on V
DD
Supply relative to V
SS
Voltage on V
DDQ
Supply relative to V
SS
VIN (DQx)
VIN (Inputs)
Storage Temperature (BGA)
Short Circuit Output Current
-0.5V to + 4.6V
-0.5V to + 4.6V
-0.5V to V
DDQ
+ 0.5V
-0.5V to V
DD
+ 0.5V
-55°C to + 150°C
100 mA
*Stress greaterthan those listed under"Absolute MaximumRatings"may cause
permanent damage to the device. This is a stress rating only, and functional
operationof the device at these orany otherconditions greaterthanthose
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximumrating conditions forextended perods may affect reliability.
NOTES:
1. IDD is specified with no output current and increases with fastercycle times. IDD increases with fastercycle times and greateroutput loading.
2. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device is active (not in power-down
mode).
NOTES:
1. All voltages referenced to Vss (GND).
Description
Conditions
Device selected; All inputs
≤
VIL or
≥
VIH;
Cycle time
≥
tKC MIN; VDD = MAX; Outputs open
Device deselected; VDD = MAX; All inputs
≤
Vss + 0.2
Device deselected; VDD = MAX; All inputs
≤
Vss +
0.2 or
≥
VDD -0.2; Cycle time
≥
tKC MIN; ADSC,
ADSP, GW, BWx, ADV,
≥
VIH
100 MHz
133 MHz 150 MHz 160 MHz 200 MHz Units
Notes
Power Supply
Current: Operating
IDD
600
750
950
950
1050
mA
1.2
CMOS Standby
ISB2
20
20
20
20
20
mA
2
Clock Running
ISB4
170
180
220
220
240
mA
2
NOTES:
1. This parameter is guaranteed by design but not tested.
2. Common Inputs = zz, ADV, ADSP, GW, ADSC, MODE, BWE
BGA T
HERMAL
R
ESISTANCE
Description
Junction to Ambient
(No Airflow)
Junction to Ball
Junction to Case (Top)
NOTE 1: Refer to BGA Thermal Resistance Correlation
application note at www.whiteedc.com in the application
notes section for modeling conditions.
Symbol Max
Theta JA 30.5
Units
Notes
1
0
C/W
Theta JB 17.3
Theta JC
0
C/W
1
1
9.8
0
C/W