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參數(shù)資料
| 型號： | WEDPZ512K72V-XBX |
| 英文描述： | NBL SSRAM MCP |
| 中文描述： | NBL的的SSRAM MCP的 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 227K |
| 代理商： | WEDPZ512K72V-XBX |
3
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPZ512K 72S-X BX
BURST SEQUENCE TABLE
NOTE 1: LBO pin must be tied to High orLow, and Foating State must not be allowed.
Write operation occurs when WE is driven low at the
rising edge of the clock. BW[h:a] can be used for byte
write operation. The pipe-lined ZBL SSRAM uses a
late-late write cycle to utilize 100% of the bandwidth. At
the first rising edge of the clock, WE and address are
registered, and the data associated with that address
is required two cycles later.
Subsequent addresses are generated by ADV High for
the burst access as shown below. The starting point of
the burst seguence is provided by the external address.
The burst address counter wraps around to its initial
state upon completion. The burst sequence is deter-
mined by the state of the LBO pin. When this pin is low,
linear burst sequence is selected. And when this pin is
high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When
ZZ is driven high, the SRAM will enter a Power Sleep
Mode after two cycles. At this time, internal state of the
SRAM is preserved. When ZZ returns to low, the SRAM
operates after two cycles of wake up time.
(Interleaved Burst, LBO = High)
Case 1
Case 2
LBO Pin High A1
A0
A1
First Address
0
0
0
1
1
0
Fourth Address
1
1
Case 3
A1
1
1
0
0
Case 4
A1
1
1
0
0
A0
1
0
1
0
A0
0
1
0
1
A0
1
0
1
0
0
0
1
1
(Linear Burst, LBO = Low)
Case 2
Case 3
A1
A0
A1
0
1
1
1
0
1
1
1
0
0
0
0
Case 1
Case 4
A1
1
0
0
1
LBO Pin High A1
First Address
A0
0
1
0
1
A0
0
1
0
1
A0
1
0
1
0
0
0
1
1
Fourth Address
The WEDPZ512K72S-XBX is an ZBL SSRAM designed
to sustain 100% bus bandwidth by eliminating turn-
around cycle when there is transition from Read to
Write, or vice versa. All inputs (with the exception of OE,
LBO and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the
ADV input. Subsequent burst addresses can be inter-
nally generated by the burst advance pin (ADV). ADV
should be driven to Low once the device has been
deselected in order to load a new address for next
operation.
Clock Enable (CKE) pin allows the operation of the
chip to be suspended as long as necessary. When
CKE is high, all synchronous inputs are ignored and
the internal device registers will hold their previous
values. NBL SSRAM latches external address and ini-
tiates a cycle when CKE and ADV are driven low at the
rising edge of the clock.
Output Enable (OE) can be used to disable the output at
any given time. Read operation is initiated when at the
rising edge of the clock, the address presented to the
address inputs are latched in the address register, CKE
is driven low, the write enable input signals WE are
driven high, and ADV driven low. The internal array is
read between the first rising edge and the second ris-
ing edge of the clock and the data is latched in the out-
put register. At the second clock edge the data is driven
out of the SRAM. During read operation OE must be
driven low for the device to drive out the requested data.
FUNCTION DESCRIPTION
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