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參數(shù)資料
| 型號： | WEDPZ512K72V-XBX |
| 英文描述： | NBL SSRAM MCP |
| 中文描述： | NBL的的SSRAM MCP的 |
| 文件頁數(shù)： | 6/14頁 |
| 文件大?。?/td> | 227K |
| 代理商： | WEDPZ512K72V-XBX |
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPZ512K 72S-X BX
AC C
HARACTERISTICS
(-55°C - T
A
- +125°C)
NOTES:
1. All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV is sampled low
and CSx is sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this
device is chip selected.
2. Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled.
3. A write cycle is defined by WE low having been registered into the device at ADV Low. A Read cycle is defined by WE
High with ADV Low. Both cases must meet setup and hold times.
O
UTPUT
L
OAD
(A)
O
UTPUT
L
OAD
(B)
(FOR T
LZC
, T
LZOE
, T
HZOE
,
AND
T
HZC
)
Dout
Zo=50
RL=50
VL=1.25V
50pF*
Dout
1538
5pF*
+2.5V
1667
*Including Scope and Jig Capacitance
AC T
EST
C
ONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
Value
0 to 2.5V
1.0V/ns
1.25V
See Output Load (A & B)
Symbol
150MHz
Min
6.7
--
--
1.5
1.5
0.0
--
--
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
133MHz
Min
7.5
--
--
1.5
1.5
0.0
--
--
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
100MHz
Min
10.0
--
--
1.5
1.5
0.0
--
--
3.0
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
Parameter
Clock Time
Clock Access Time
Output enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
CKE Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High
Address Advance to Clock High
Chip Select Setup to Clock High
Address Hold to Clock high
CKE Hold to Clock High
Data Hold to Clock High
Write Hold to Clock High
Address Advance to Clock High
Chip Select Hold to Clock High
Max
Max
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CYC
t
CD
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
CH
t
CL
t
AS
t
CES
t
DS
t
WS
t
ADVS
t
CSS
t
AH
t
CEH
t
DH
t
WH
t
ADVH
t
CSH
3.8
3.8
--
--
--
3.0
3.0
--
--
--
--
--
--
4.2
4.2
--
--
--
3.5
3.5
--
--
--
--
--
--
5.0
5.0
--
--
--
3.5
3.5
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
---
--
--
--
--
--
--
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