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參數資料
| 型號： | WM8722 |
| 廠商： | Wolfson Microelectronics |
| 英文描述： | Stereo DAC with Integrated Tone Generator and Line/Variable Level Outputs |
| 中文描述： | 立體聲DAC，具有集成的音調發(fā)生器和線/變平輸出 |
| 文件頁數： | 11/23頁 |
| 文件大?。?/td> | 438K |
| 代理商： | WM8722 |
Advanced Information
WM8722
WOLFSON MICROELECTRONICS LTD
AI Rev 1.5 May 2000
11
SYSTEM CLOCK FREQUENCY (MHZ)
256fs
8.192
11.2896
12.288
24.576
SAMPLING RATE
(LRCIN)
384fs
12.288
16.9340
18.432
36.864
32kHz
44.1kHz
48kHz
96kHz
Table 1 System Clock Frequencies versus Sampling Rate
AUDIO DATA INTERFACE
The serial data interface to WM8722 is fully compatible with both normal (MSB first, right-justified) or
I
S interfaces. Data may be packed (number of serial BLCKS per LRCIN period is exactly 2 times the
number of data bits, i.e. normally 32 in 16 bit mode) or unpacked (more than 32 BCLKs per LRCIN
period.
The WM8722 will automatically detect 16-bit packed data being sent to the device in normal mode,
and accept the data in this input format accordingly.
I
2
S MODE
0
1
DESCRIPTION
Normal format (MSB-first, right justified)
I
2
S format (Philips serial data protocol )
Table 2. Serial Interface Formats
MSB
MSB
LSB
LSB
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1/fs
1
2
3
n
n-1
n-2
1
2
3
n
n-1
n-2
Figure 5. Normal Data Input Timing
MSB
MSB
LSB
LSB
LEFT CHANNEL
RIGHT CHANNEL
LRCIN
BCKIN
DIN
1/fs
1
2
3
n
n-1
n-2
1
2
3
n
n-1
n-2
Figure 6. I
2
S Data Input Timing
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