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參數(shù)資料
| 型號(hào)： | WV3DG72256V10AD2I-MG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 256M X 72 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168 |
| 封裝： | ROHS COMPLIANT, DIMM-168 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 274K |
| 代理商： | WV3DG72256V10AD2I-MG |
WV3DG72256V-AD2
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
January 2006
Rev. 0
OPERATING AC PARAMETER
Parameter
Symbol
133/100
Units
Notes
Min
Max
CLK cycle time
CAS latency = 3
tCC
7.5
1,000
ns
1
CAS latency = 2
–
CLK to valid output delay
CAS latency = 3
tSAC
5.4
ns
1, 2
CAS latency = 2
–
Output data hold time
CAS latency = 3
tOH
3
ns
2
CAS latency = 2
–
CLK high pulse width
tCH
2.5
ns
3
CLK low pulse width
tCL
2.5
ns
3
Input setup time
tSS
1.5
ns
3
Input hold time
tSH
0.8
ns
3
CLK to output in Low-z
tSLZ
1ns
2
CLK to output in Hi-z
CAS latency = 3
tHZ
5.4
ns
CAS latency = 2
–
Notes: 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns. If tr &tf is longer than 1ns, transient time
compensation should be considered, i.e., [(tr = tf)/2-1]ns should be added to the parameter.
PRELIMINARY*
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