參數(shù)資料
型號(hào): X1203S8
英文描述: IC-SMD-RTC WITH EEPROM
中文描述: 集成電路表面貼裝與EEPROM的時(shí)鐘
文件頁(yè)數(shù): 1/20頁(yè)
文件大?。?/td> 88K
代理商: X1203S8
9900-3002.1 4/28/00 EP
Xicor, Inc. 2000 Patents Pending
Characteristics subject to change without notice.
1 of 20
X1203
2-Wire
RTC
Real Time Clock/Calendar/Alarm
FEATURES
2 Alarms—Interrupt Output
—Settable on the second, 10s of seconds,
minute, 10s of minutes, hour, day, month, or
day of the week
—Repeat alarm for time base generation
2 Wire interface interoperable with I
—400kHz data transfer rate
Secondary Power Supply Input with internal
Switch-Over Circuitry
Year 2000 Compliant
Low Power CMOS
—<1μA operating current
—<3μA active current during program
—<400μA active current during data read
Typical Nonvolatile Write Cycle Time: 5ms
High Reliability
—100,000 endurance cycles
—Guaranteed data retention: 100 years
Small Package Options
—8-lead SOIC package, 8-lead TSSOP package
2
C
DESCRIPTION
The X1203 is a Real Time Clock with clock/calendar
circuits and two alarms. The dual port clock and alarm
registers allow the clock to operate, without loss of
accuracy, even during read and write operations.
The clock/calendar provides functionality that is con-
trollable and readable through a set of registers. The
clock, using a low cost 32.768kHz crystal input, accu-
rately tracks the time in seconds, minutes, hours, date,
day, month and years. It has leap year correction,
automatic adjustment for the year 2000 and months
with less than 31 days.
An alarm match of the RTC sets an interrupt flag and
activates an interrupt pin. An alternative alarm function
provides a pulsed interrupt for long time constant time-
bases.
The device offers a backup power input pin. This
Vback pin allows the device to be backed up by a non-
rechargeable battery. The RTC is fully operational from
2.5 to 6 volts.
BLOCK DIAGRAM
X1
X2
Oscillator
Frequency
Divider
Timer
Calendar
Logic
8
32.768kHz
Control
Registers
1Hz
Time
Keeping
Registers
(SRAM)
Alarm Regs
(EEPROM)
Compare
M
IRQ
Control
Decode
Logic
Alarm
(EEPROM)
SCL
SDA
Serial
Interface
Decoder
Interrupt Enable
Registers
Status
(SRAM)
Alarm
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