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參數(shù)資料
| 型號： | X1203S8 |
| 英文描述： | IC-SMD-RTC WITH EEPROM |
| 中文描述： | 集成電路表面貼裝與EEPROM的時鐘 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 88K |
| 代理商： | X1203S8 |
X1203
Characteristics subject to change without notice.
3 of 20
in a sequential read mode. Since the clock runs contin-
uously and a read takes a finite amount of time, there
is the possibility that the clock could change during the
course of a read operation. In this device, the time is
latched by the read command (falling edge of the clock
on the ACK bit prior to RTC data output) into a seper-
ate latch to avoid time changes during the read opera-
tion. The clock continues to run. Alarms occuring
during a read are unaffected by the read operation.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC reg-
isters. To avoid changing the current time by an uncom-
pleted write operation, the current time value is loaded
into a separate buffer at the falling edge of the clock on
the ACK bit before the RTC data input bytes, the clock
continues to run. The new serial input data replaces the
values in the buffer. This new RTC value is loaded back
into the RTC register by a stop bit at the end of a valid
write sequence. An invalid write operation aborts the
time update procedure and the contents of the buffer are
discarded. After a valid write operation the RTC will
reflect the newly loaded data beginning with the first
“one second” clock cycle after the stop bit. The RTC
continues to update the time while an RTC register write
is in progress and the RTC continues to run during any
nonvolatile write sequences. A single byte may be writ-
ten to the RTC without affecting the other bytes.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area log-
ically separated from the array and are only accessible
following a slave byte of “1101111x” and reads or
writes to addresses [0000h:003Fh].
CCR Access
The contents of the CCR can be modified by performing
a byte or a page write operation directly to any address
in the CCR. Prior to writing to the CCR (except the status
register), however, the WEL and RWEL bits must be
set using a two step process (See section “Writing to
the Clock/Control Registers.”)
The CCR is divided into 5 sections. These are:
1. Alarm 0
2. Alarm 1
3. Control
4. Real Time Clock
5. Status
Sections 1) through 3) are nonvolatile and Sections 4)
and 5) are volatile. Each register is read and written
through buffers. The non-volatile portion (or the counter
portion of the RTC) is updated only if RWEL is set and
after a valid write operation and stop bit. A sequential
read or page write operation provides access to the
contents of only one section of the CCR per operation.
Access to another section requires a new operation.
Continued reads or writes, once reaching the end of a
section, will wrap around to the start of the section. A
read or page write can begin at any address in the CCR.
Section 5) is a volatile register. It is not necessary to
set the RWEL bit prior to writing the status register.
Section 5) supports a single byte read or write only.
Continued reads or writes from this section terminates
the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read. The
read instruction latches all Clock registers into a buffer,
so an update of the clock does not change the time
being read. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next register.
ALARM REGISTERS
There are two alarm registers whose contents mimic
the contents of the RTC register, but add enable bits
and exclude the 24 hour time selection bit. The enable
bits specify which registers to use in the comparison
between the alarm and real time registers. For example:
– The user can set the X1203 to alarm every Wednesday
at 8:00 AM by setting the EDWn, the EHRn and EMNn
enable bits to ‘1’ and setting the DWAn, HRAn and
MNAn Alarm registers to 8:00 AM Wednesday.
– A daily alarm for 9:30PM results when the EHRn and
EMNn enable bits are set to ‘1’ and the HRAn and
MNAn registers set 9:30 PM.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X1203S8I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| X1203V8 | 制造商:Intersil Corporation 功能描述: |
| X-120-499 | 制造商:Brady Corporation 功能描述:VIAL SIDE/TOP COMBO-B499 .50X1X.375DIA |
| X1205 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Real Time Clock/Calendar |
| X1205S8 | 功能描述:IC RTC/CALENDAR 2-WIRE 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 實時時鐘 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:時鐘/日歷 特點:警報器，閏年，SRAM 存儲容量:- 時間格式:HH:MM:SS（12/24 小時） 數(shù)據(jù)格式:YY-MM-DD-dd 接口:SPI 電源電壓:2 V ~ 5.5 V 電壓 - 電源，電池:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-TDFN EP 包裝:管件 |
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