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參數(shù)資料
| 型號(hào)： | X1203S8T1 |
| 元件分類： | XO, clock |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO8 |
| 封裝： | PLASTIC, SOIC-8 |
| 文件頁(yè)數(shù)： | 15/19頁(yè) |
| 文件大小： | 155K |
| 代理商： | X1203S8T1 |
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X1203
Characteristics subject to change without notice.
5 of 19
REV 1.2.0 2/13/01
www.xicor.com
REAL TIME CLOCK REGISTERS
Year 2000 (Y2K)
The X1203 has a century byte that “rolls over” from 19
to 20 when the years byte changes from 99 to 00. The
Y2K byte can contain only the values of 19 or 20.
Day of the Week Register (DW)
This register provides a Day of the week status and
uses three bits DY2 to DY0 to represent the seven days
of the week. The counter advances in the cycle 0-1-2-
3-4-5-6-0-1-2-... The assignment of a numerical value
to a specic day of the week is arbitrary and may be
decided by the system software designer. The Clock
Default value denes as ‘0’.
Clock/Calendar Registers (YR, MO, DT, HR, MN, SC)
These registers depict BCD representations of the
time. As such, SC (Seconds) and MN (Minutes) range
from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM
indicator (H21 bit) or 0 to 23 (with T24 = 1), DT (Date)
is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.
24-Hour Time
If the T24 bit of the HR register is 1, the RTC will use a
24-hour format. If the T24 bit is 0, the RTC will use 12-
hour format and bit H21 will function as an AM/PM indi-
cator with a ‘1’ representing PM. The clock defaults to
standard time with H21 = 0.
Leap Years
Leap years add the day February 29 and are dened
as those years that are divisible by 4. Years divisible by
100 are not leap years, unless they are also divisible
by 400. This means that the year 2000 is a leap year,
the year 2100 is not. The X1203 does not correct for
the leap year in the year 2100.
STATUS REGISTER (SR)
The status register is located in the RTC area at address
003Fh. This is a volatile register only and is used to con-
trol the WEL and RWEL write enable latches, read an
optional low voltage sense bit, and read the two alarm
bits. This register is logically separated from both the
array and the clock/control registers (CCR).
Table 2. Status Register (SR)
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from VBACK, not VCC. It is a read only bit and is set/
reset by hardware.
AL1, AL0: Alarm Bits—Volatile
These bits announce if either alarm 1 or alarm 2 match
the real time clock. If there is a match, the respective
bit is set to ‘1’. The falling edge of the last data bit in a
SR Read operation resets the ags. Note: Only the AL
bits that are set when an SR read starts will be reset.
An alarm bit that is set by an alarm occurring during an
SR read operation will remain set after the read opera-
tion is complete.
RWEL: Register Write Enable Latch—Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the clock/control registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both
the RWEL and WEL bits to be set in a specic
sequence.
WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the CCR during a
write operation. This bit is a volatile latch that powers
up in the LOW (disabled) state. While the WEL bit is
LOW, writes to the CCR will be ignored (no acknowl-
edge will be issued after the Data Byte). The WEL bit is
set by writing a “1” to the WEL bit and zeroes to the
other bits of the status register. Once set, WEL
remains set until either reset to 0 (by writing a “0” to the
WEL bit and zeroes to the other bits of the status regis-
ter) or until the part powers up again. Writes to WEL bit
do not cause a non volatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.
Addr
7
6
5
4
3
2
1
0
003Fh
BAT
AL1
AL0
x
RWEL
WEL
RTCF
Default
0
1
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