The bit is set regardless of whether VCC or V
參數(shù)資料
型號: X1227V8IZ
廠商: Intersil
文件頁數(shù): 5/28頁
文件大?。?/td> 0K
描述: IC RTC/CAL/CPU SUP EE 8-TSSOP
標(biāo)準(zhǔn)包裝: 100
類型: 時鐘/日歷
特點: 警報器,閏年,監(jiān)控器,監(jiān)視計時器
時間格式: HH:MM:SS(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 4.5 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 8-TSSOP
包裝: 管件
13
FN8099.2
May 8, 2006
The bit is set regardless of whether VCC or VBACK is
applied first. The loss of only one of the supplies does
not set the RTCF bit to “1”. On power-up after a total
power failure, all registers are set to their default
states and the clock will not increment until at least
one byte is written to the clock register. The first valid
write to the RTC section after a complete power failure
resets the RTCF bit to “0” (writing one byte is suffi-
cient).
Unused Bits:
This device does not use bits 3 or 4 in the SR, but must
have a zero in these bit positions. The Data Byte output
during a SR read will contain zeros in these bit locations.
CONTROL REGISTERS
The Control Bits and Registers, described under this
section, are nonvolatile.
Block Protect Bits—BP2, BP1, BP0
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to one of eight segments
of the array. The partitions are described in Table 3 .
Table 3. Block Protect Bits
Watchdog Timer Control Bits—WD1, WD0
The bits WD1 and WD0 control the period of the
Watchdog Timer. See Table 4 for options.
Table 4. Watchdog Timer Time-Out Options
ON-CHIP OSCILLATOR COMPENSATION
Digital Trimming Register (DTR) — DTR2, DTR1
and DTR0 (Non-Volatile)
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.
DTR2 is a sign bit. DTR2=0 means frequency
compensation is > 0. DTR2=1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
A range from -30ppm to +30ppm can be represented
by using three bits above.
Table 5. Digital Trimming Registers
BP2
BP1
BP0
Protected Addresses
X1227
Array Lock
0
None (Default)
None
00
1
180h - 1FFh
Upper 1/4
01
0
100h - 1FFh
Upper 1/2
01
1
000h - 1FFh
Full Array
10
0
000h - 03Fh
First Page
10
1
000h - 07Fh
First 2 pgs
11
0
000h - 0FFh
First 4 pgs
11
1
000h - 1FFh
First 8 pgs
WD1 WD0
Watchdog Time-Out Period
0
1.75 seconds
0
1
750 milliseconds
1
0
250 milliseconds
1
Disabled (default)
DTR Register
Estimated frequency
PPM
DTR2
DTR1
DTR0
00
0
0 (Default)
01
0
+10
00
1
+20
01
1
+30
10
0
11
0
-10
10
1
-20
11
1
-30
X1227
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