參數(shù)資料
型號: X1288V14Z
廠商: INTERSIL CORP
元件分類: XO, clock
英文描述: 2-Wire⑩ RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM
中文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO14
封裝: ROHS COMPLIANT, PLASTIC, TSSOP-14
文件頁數(shù): 11/27頁
文件大?。?/td> 425K
代理商: X1288V14Z
11
FN8102.3
April 14, 2006
ALARM REGISTERS
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
– Setting the Enable Month bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
*n = 0 for Alarm 0: N = 1 for Alarm 1
When there is a match, an alarm flag is set. The occur-
rence of an alarm can be determined by polling the
AL0 and AL1 bits or by enabling the IRQ output, using
it as hardware flag.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
– The user can set the X1288 to alarm every Wednes-
day at 8:00 AM by setting the EDWn*, the EHRn*
and EMNn* enable bits to ‘1’ and setting the DWAn*,
HRAn* and MNAn* Alarm registers to 8:00 AM
Wednesday.
– A daily alarm for 9:30PM results when the EHRn*
and EMNn* enable bits are set to ‘1’ and the HRAn*
and MNAn* registers are set to 9:30 PM.
*n = 0 for Alarm 0: N = 1 for Alarm 1
REAL TIME CLOCK REGISTERS
Clock/Calendar Registers (SSEC, SC, MN, HR, DT,
MO, YR)
These registers depict BCD representations of the
time. As such, SSEC (1/100 Second) range from 00 to
99, SC (Seconds) and MN (Minutes) range from 00 to
59, HR (Hour) is 1 to 12 with an AM or PM indicator
Table 1. Clock/Control Memory Map
Addr.
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
000F
000E
000D
000C
000B
000A
0009
0008
0007
Type
Status
RTC
(SRAM)
Reg
Name
SR
SSEC
DW
YR
MO
DT
HR
MN
SC
DTR
ATR
INT
BL
Y2K1
DWA1
YRA1
MOA1
DTA1
HRA1
MNA1
SCA1
Y2K0
Bit
Range
D
01h
xxh
xxh
xxh
xxh
xxh
xxh
xxh
xxh
00h
00h
00h
18h
20h
00h
7
6
5
4
0
3
0
2
1
0
(optional)
RTCF
SS10
DY0
Y10
G10
D10
H10
M10
S10
DTR0
ATR0
BAT
SS23
0
Y23
0
0
MIL
0
0
0
0
IM
BP2
AL1
SS22
0
Y22
0
0
0
M22
S22
0
0
AL1E
BP1
AL0
SS21
0
Y21
0
D21
H21
M21
S21
0
ATR5
AL0E
BP0
RWEL
SS12
DY2
Y12
G12
D12
H12
M12
S12
DTR2
ATR2
Read Only Read Only Read Only
Read Only Read Only Read Only
WEL
SS11
DY1
Y11
G11
D11
H11
M11
S11
DTR1
ATR1
SS20
0
Y20
G20
D20
H20
M20
S20
0
ATR4
FO1
WD1
Read-only - Default = 20h
0
SS13
0
Y13
G13
D13
H13
M13
S13
0
ATR3
FO0
WD0
0-99
0-6
0-99
1-12
1-31
0-23
0-59
0-59
Control (EE-
PROM)
Alarm1
(EEPROM)
20
0-6
EDW1
0
0
0
DY2
DY1
DY0
Unused - Default = RTC Year value (No EEPROM) - Future expansion
0
0
A1G20
0
A1D21
A1D20
0
A1H21
A1H20
A1M22
A1M21
A1M20
A1S22
A1S21
A1S20
Read-only - Default = 20h
EMO1
EDT1
EHR1
EMN1
ESC1
A1G13
A1D13
A1H13
A1M13
A1S13
A1G12
A1D12
A1H12
A1M12
A1S12
A1G11
A1D11
A1H11
A1M11
A1S11
A1G10
A1D10
A1H10
A1M10
A1S10
1-12
1-31
0-23
0-59
0-59
20
00h
00h
00h
00h
00h
20h
Alarm0
(EEPROM)
0006
0005
0004
0003
0002
0001
0000
DWA0
YRA0
MOA0
DTA0
HRA0
MNA0
SCA0
EDW0
0
0
0
0
DY2
DY1
DY0
0-6
00h
Unused - Default = RTC Year value (No EEPROM) – Future expansion
0
0
A0G20
0
A0D21
A0D20
0
A0H21
A0H20
A0M22
A0M21
A0M20
A0S22
A0S21
A0S20
EMO0
EDT0
EHR0
EMN0
ESC0
A0G13
A0D13
A0H13
A0M13
A0S13
A0G12
A0D12
A0H12
A0M12
A0S12
A0G11
A0D11
A0H11
A0M11
A0S11
A0G10
A0D10
A0H10
A0M10
A0S10
1-12
1-31
0-23
0-59
0-59
00h
00h
00h
00h
00h
X1288
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