參數(shù)資料
型號(hào): X24001SI-3
英文描述: Identi⑩PROM
中文描述: 認(rèn)⑩胎膜早破
文件頁(yè)數(shù): 8/13頁(yè)
文件大?。?/td> 47K
代理商: X24001SI-3
8
X24001
Bus Timing
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tLOW
tSU:STO
tR
tBUF
SCL
SDA IN
SDA OUT
tDH
tAA
tF
tHIGH
3830 FHD F09
WRITE CYCLE LIMITS
Symbol
Parameter
Min.
Max.
Units
t
WR(4)
Write Cycle Time
5
ms
3830 PGM T09
Write Cycle Timing
Note:
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.
(4) The write cycle time is the time from the initiation of a write sequence to the end of the internal erase/program cycle. During the
write cycle, the X24001 bus interface circuits are disabled, SDA is high impedance, and the device does not respond to start
conditions.
3830 ILL F10.1
SDA
tWR
SCL
D0
START
CONDTION
X24001
ADDRESS
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