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參數(shù)資料
| 型號： | X24026X-2.7 |
| 英文描述： | Serial E2PROM |
| 中文描述： | 串行E2PROM |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 64K |
| 代理商： | X24026X-2.7 |
X24026
5
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave are the device type identifier (see
Figure 4). For the X24026 this is fixed as 1010[B].
Figure 4. Slave Address
The next three significant bits are reserved address bits.
The last bit of the slave address defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operations is selected.
Following the start condition, the X24026 monitors the
SDA bus comparing the slave address being transmitted
with its slave address. Upon a correct compare the
X24026 outputs an acknowledge on the SDA line.
Depending on the state of the R/W bit, the X24026 will
execute a read or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24026 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of
the 256 words of memory. Upon receipt of the word
address the X24026 responds with an acknowledge, and
awaits the next eight bits of data, again responding with
an acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the X24026
begins the internal write cycle to the nonvolatile memory.
While the internal write cycle is in progress the X24026
inputs are disabled, and the device will not respond to
any requests from the master. Refer to Figure 5 for the
address, acknowledge and data transfer sequence.
Figure 5. Byte Write
Figure 6. Page Write
1
7020 FRM 06
0
1
0
0
0
0
R/W
DEVICE TYPE
IDENTIFIER
RESERVE
ADDRESS
BITS
BUS ACTIVITY:
MASTER
SDA LINE
X24026
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
P
A
C
K
A
C
K
A
C
K
WORD
ADDRESS
DATA
7020 FRM 07
BUS ACTIVITY:
BUS ACTIVITY:
MASTER
SDA LINE
X24026
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
WORD
ADDRESS (n)
DATA n
DATA n+1
DATA n+3
NOTE:In this example n = xxxx 000 (B); x = 1 or 0
7020 FRM 08
BUS ACTIVITY:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X24026 | IC CTRL/REG SYNC BUCK 24-MLPQ |
| X24026X | IC CTRL/REG SYNC BUCK 24-TSSOP |
| X24026Y | Controller IC; Package/Case:24-MLPQ; Supply Voltage Max:28V; Controller Type, IC:Buck; Features:Synchronous Buck, Voltage Mode, Dual PWM, High Performance; Leaded Process Compatible:Yes; Number of PWM Channels:2 |
| X24026H | Serial E2PROM |
| X24026W | Serial E2PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X24026Y | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Serial E2PROM |
| X24026Y-2.7 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X2402DI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial EEPROM |
| X2402I | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Electrically Erasable PROM |
| X2402P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial EEPROM |
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