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參數(shù)資料
| 型號： | X24026X-2.7 |
| 英文描述： | Serial E2PROM |
| 中文描述： | 串行E2PROM |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 64K |
| 代理商： | X24026X-2.7 |
X24026
6
Page Write
The X24026 is capable of a four byte page write opera-
tion. It is initiated in the same manner as the byte write
operation, but instead of terminating the write cycle after
the first data word is transferred, the master can transmit
up to three more words. After the receipt of each word,
the X24026 will respond with an acknowledge.
After the receipt of each word, the two low order address
bits are internally incremented by one. The high order six
bits of the address remain constant. If the master should
transmit more than four words prior to generating the
stop condition, the address counter will “roll over” and the
previously written data will be overwritten. As with the
byte write operation, all inputs are disabled until comple-
tion of the internal write cycle. Refer to Figure 6 for the
address, acknowledge and data transfer sequence.
Acknowledge Polling
The disabling of the inputs, during the internal write oper-
ation, can be used to take advantage of the typical 5 ms
write cycle time. Once the stop condition is issued to indi-
cate the end of the host’s write operation the X24026 ini-
tiates the internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition fol-
lowed by the slave address for a write operation. If the
X24026 is still busy with the write operation no ACK will
be returned. If the X24026 has completed the write oper-
ation an ACK will be returned and the master can then
proceed with the next read or write operation.
READ OPERATIONS
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of the
slave address is set to a one. There are three basic read
operations: current address read, random read and
sequential read.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read opera-
tion, the master must either issue a stop condition during
the ninth cycle or hold SDA HIGH during the ninth clock
cycle and then issue a stop condition.
Flow 1. ACK Polling Sequence
7020 FRM 09
WRITE OPERATION
COMPLETED
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE_
ADDRESS AND R/W = 0
ACK
RETURNED
NEXT
OPERATION
A WRITE
ISSUE BYTE
ADDRESS
PROCEED
ISSUE STOP
NO
YES
YES
PROCEED
ISSUE STOP
NO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X24026 | IC CTRL/REG SYNC BUCK 24-MLPQ |
| X24026X | IC CTRL/REG SYNC BUCK 24-TSSOP |
| X24026Y | Controller IC; Package/Case:24-MLPQ; Supply Voltage Max:28V; Controller Type, IC:Buck; Features:Synchronous Buck, Voltage Mode, Dual PWM, High Performance; Leaded Process Compatible:Yes; Number of PWM Channels:2 |
| X24026H | Serial E2PROM |
| X24026W | Serial E2PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X24026Y | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Serial E2PROM |
| X24026Y-2.7 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X2402DI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial EEPROM |
| X2402I | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Electrically Erasable PROM |
| X2402P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial EEPROM |
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