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參數(shù)資料
| 型號： | X24325VM-2.7 |
| 英文描述： | Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection |
| 中文描述： | 先進(jìn)的2線串行e的2座門鎖TM保護(hù)胎膜早破 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 79K |
| 代理商： | X24325VM-2.7 |
X24325
10
Block Protect Bits
The Block Protect Bits BP0 and BP1 determine which
blocks of the memory are write-protected:
Programmable Hardware Write Protect
The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the Write Protect Register
control the programmable hardware write protect
feature. Hardware write protection is enabled when the
WP pin and the WPEN bit are both HIGH, and
disabled when either the WP pin is LOW or the WPEN
bit is LOW. When the chip is hardware write-protected,
nonvolatile writes are disabled to the Write Protect
Register, including the BP bits and the WPEN bit itself,
as well as to block-protected sections in the memory
array. Only the sections of the memory array that are
not block-protected can be written. Note that since the
WPEN bit is write-protected, it cannot be changed
back to a LOW state, and write protection is disabled
as long as the the WP pin is held HIGH. Table 2
defines the write protection status for each state of
WPEN and WP.
Table 1. Block Protect Bits
6552 FRM T02
BP1
0
0
1
BP0
0
1
0
Protected
Addresses
None
C00h–FFFh
800h–FFFh
Upper 1/4
Upper 1/2
Full Array (WPR
not included)
1
1
0000h–FFFh
Table 2. Write Protect Status Table
6552 FRM T03
WP
0
X
1
WPEN
X
0
1
Memory Array
(Not Block
Protected)
Writable
Writable
Writable
Memory Array
(Block Protected)
Protected
Protected
Protected
BP Bits
Writable
Writable
Protected
WPEN Bit
Writable
Writable
Protected
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X24325P-2.7 | Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection |
| X24325 | Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection |
| X24325P | Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection |
| X24325PI | IC ADJ SHUNT REG LV SOT-23-3 |
| X24325PM | IC ADJ SHUNT REG LV SOT-23-3 |
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