參數(shù)資料
型號(hào): X24645S8M-2.7
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Isolated Flyback Switching Regulator with 9V Output
中文描述: 隔離反激式開(kāi)關(guān)穩(wěn)壓9V輸出
文件頁(yè)數(shù): 8/18頁(yè)
文件大?。?/td> 84K
代理商: X24645S8M-2.7
X24645
8
Figure 10. Typical System Configuration
Sequential Read
Sequential reads can be initiated as either a current
address read or random access read. The first byte is
transmitted as with the other modes, however, the
master now responds with an acknowledge, indicating
it requires additional data. The X24645 continues to
output data for each acknowledge received. The read
operation is terminated by the master; by not
responding with an acknowledge and then issuing a
stop condition.
The data output is sequential, with the data from
address n followed by the data from n + 1. The address
counter for read operations increments all address bits,
allowing the entire memory contents to be serially read
during one operation. At the end of the address space
(address 8191), the counter “rolls over” to 0 and the
X24645 continues to output data for each acknowledge
received. Refer to Figure 9 for the address,
acknowledge and data transfer sequence.
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24645
SLAVE
ADDRESS
A
C
K
2783 ILL F13
A
C
K
DATA n+x
S
T
O
P
P
DATA n
A
C
K
DATA n+1
A
C
K
DATA n+2
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
PULL-UP
RESISTORS
SDA
SCL
VCC
2783 ILL F14
Figure 9. Sequential Read
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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