參數(shù)資料
型號: X24645VM
英文描述: Voltage Regulator IC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes
中文描述: 先進(jìn)的2線串行e的2座門鎖TM保護(hù)胎膜早破
文件頁數(shù): 1/18頁
文件大?。?/td> 84K
代理商: X24645VM
Advanced 2-Wire Serial E
2
PROM with Block Lock
TM
Protection
64K
8192 x 8 Bit
Preliminary Information
2783-3.5 5/13/96 T1/C0/D0 NS
Xicor, 1995, 1996 Patents Pending
Characteristics subject to change without notice
1
X24645
FUNCTIONAL DIAGRAM
FEATURES
2.7V to 5.5V Power Supply
Low Power CMOS
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1
Internally Organized 8192 x 8
New Programmable Block Lock Protection
—Software Write Protection
—Programmable hardware Write Protect
Block Lock (0, 1/4, 1/2, or all of the E
array)
2 Wire Serial Interface
Bidirectional Data Transfer Protocol
32 Byte Page Write Mode
—Minimizes Total Write Time Per Byte
Self Timed Write Cycle
—Typical Write Cycle Time of 5ms
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
Available Packages
—8-Lead PDIP
—8-Lead SOIC (JEDEC)
—14-Lead SOIC (JEDEC)
—20-Lead TSSOP
μ
A
2
PROM
DESCRIPTION
The X24645 is a CMOS 65,536-bit serial E
internally organized 8192 x 8. The X24645 features a
serial interface and software protocol allowing opera-
tion on a simple two wire bus.
2
PROM,
Two device select inputs (S
devices to share a common two wire bus.
1
, S
2
) allow up to four
A Write Protect Register at the highest address loca-
tion, 1FFFh, provides three new write protection
features: Software Write Protect, Block Write Protect,
and Hardware Write Protect. The Software Write
Protect feature prevents any nonvolatile writes to the
X24645 until the WEL bit in the write protect register is
set. The Block Write Protection feature allows the user
to individually write protect four blocks of the array by
programming two bits in the write protect register. The
Programmable Hardware Write Protect feature allows
the user to install the X24645 with WP tied to V
program the entire memory array in place, and then
enable the hardware write protection by programming
a WPEN bit in the write protect register. After this,
selected blocks of the array, including the write protect
register itself, are permanently write protected, as long
as WP remains HIGH.
CC
,
START
STOP
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER
+COMPARATOR
H.V. GENERATION
TIMING &
CONTROL
WORD
ADDRESS
COUNTER
XDEC
YDEC
DOUT
ACK
E
2
PROM
256 X 256
DATA REGISTER
START CYCLE
VCC
VSS
R/W
PIN
SDA
SCL
S2
S1
DOUT
LOAD
INC
CK
8
2783 ILL F01
WRITE PROTECT
REGISTER AND
LOGIC
WP
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