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參數資料
| 型號： | X24645VM |
| 英文描述： | Voltage Regulator IC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | 先進的2線串行e的2座門鎖TM保護胎膜早破 |
| 文件頁數： | 3/18頁 |
| 文件大小： | 84K |
| 代理商： | X24645VM |
X24645
3
Figure 1. Data Validity
Figure 2. Definition of Start and Stop
DEVICE OPERATION
The X24645 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the X24645 will be considered a slave in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24645 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
SCL
SDA
DATA STABLE
DATA
CHANGE
2783 ILL F04
SCL
SDA
START BIT
STOP BIT
2783 ILL F05
Notes:
(5) Typical values are for T
(6) t
WR
is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the
device requires to perform the internal write operation.
A
= 25
°
C and nominal supply voltage (5V)
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