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參數(shù)資料
| 型號： | X25F128SE-5 |
| 英文描述： | SerialFlash⑩ Memory With Block Lock⑩ Protection |
| 中文描述： | SerialFlash⑩內(nèi)存區(qū)塊可鎖定的⑩保護 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 61K |
| 代理商： | X25F128SE-5 |
X25F128
3
formatted as follows:
PPEN, BL0, and BL1 are set by the PRSR instruction.
PEL and PIP are “read-only” and automatically set by
other operations.
The Programming-In-Process (PIP) bit indicates
whether the X25F128 is busy with a program operation.
When set to a “1” programming is in progress, when
set to a “0” no programming is in progress. During
programming, all other bits are set to “1”.
The Program Enable Latch (PEL) bit indicates the
status of the program enable latch. When set to a “1” the
latch is set; when set to a “0” the latch is reset.
The Block Lock (BL0 and BL1) bits are nonvolatile and
allow the user to select one of four levels of protection.
The X25F128 array is divided into four equal segments.
One, two, or all four of the segments may be locked. That
is, the user may read the segments, but will be unable to
alter (program) data within the selected segments. The
partitioning is controlled as illustrated below.
Status Register Bits
BL1
Array Addresses
Locked
BL0
0
0
1
1
0
1
0
1
None
upper fourth
upper half
All
6829 PGM T03.1
Program-Protect Enable
The Program-Protect-Enable bit (PPEN) in the
X25F128 status register acts as an enable bit for the
PP
pin.
PRINCIPLES OF OPERATION
The X25F128 is a SerialFlash Memory designed
to interface directly with the synchronous serial periph-
eral interface (SPI) of many popular microcontroller
families.
The X25F128 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising SCK.
CS
must be LOW and the
HOLD
and
PP
inputs must be HIGH during the entire operation. The
PP
input is “Don’t Care” if PPEN is set “0”.
Table 1 contains a list of the instructions and their
operation codes. All instructions, addresses and data
are transferred MSB first.
Data input is sampled on the first rising edge of SCK after
CS
goes LOW. SCK is static, allowing the user to stop
the clock and then resume operations. If the clock line is
shared with other peripheral devices on the SPI bus, the
user can assert the
HOLD
input to place the X25F128
into a “PAUSE” condition. After releasing
HOLD
, the
X25F128 will resume operation from the point when
HOLD
was first asserted.
Program Enable Latch
The X25F128 contains a program enable latch. This
latch must be SET before a program operation will be
completed internally. The PREN instruction will set the
latch and the PRDI instruction will reset the latch. This
latch is automatically reset on power-up and after the
completion of a sector program or status register write
cycle.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a program cycle. The status register is
7
6
X
5
X
4
X
3
2
1
0
PPEN
BL1
BL0
PEL
PIP
6829 PGM T02
Table 1. Instruction Set
Instruction Name
PREN
PRDI
RDSR
PRSR
READ
Instruction Format*
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
Operation
Set the Program Enable Latch (Enable Program Operations)
Reset the Program Enable Latch (Disable Program Operations)
Read Status Register
Program Status Register
Read from Memory Array beginning at Selected Address
Program Memory Array beginning at Selected Address
(32 Bytes)
PROGRAM
0000 0010
6829 PGM T04.1
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| X25F128SI | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:SerialFlash⑩ Memory With Block Lock⑩ Protection |
| X25F128SI-5 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:SerialFlash⑩ Memory With Block Lock⑩ Protection |
| X25FG | 制造商:VMI 制造商全稱:VMI 功能描述:2,500 V - 10,000 V Rectifiers 100 mA - 250 mA Forward Current 200 ns Recovery Time |
| X25M000000S054 | 制造商:AEL Crystals Limited 功能描述:CRYSTAL SM 25MHZ 2.5X2 |
| X25RT | 制造商:Burndy 功能描述:HARDWARE TOOLS, BURNDY PRODUCTS TOOLING |
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