參數(shù)資料
型號(hào): X28C512JIZ-15
廠商: INTERSIL CORP
元件分類: DRAM
英文描述: 5V, Byte Alterable EEPROM
中文描述: 64K X 8 EEPROM 5V, 150 ns, PQCC32
封裝: ROHS COMPLIANT, PLASTIC, MS-016AE, LCC-32
文件頁數(shù): 14/21頁
文件大?。?/td> 473K
代理商: X28C512JIZ-15
14
FN8106.2
June 7, 2006
WE Controlled Write Cycle
NOTE:
4. t
WC
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device
requires to complete the internal write operation.
Write Cycle Limits
SYMBOL
PARAMETER
MIN
MAX
UNIT
t
WC
(Note 4)
Write cycle time
10
ms
t
AS
Address setup time
0
ns
t
AH
Address hold time
50
ns
t
CS
Write setup time
0
ns
t
CH
Write hold time
0
ns
t
CW
CE pulse width
100
ns
t
OES
OE HIGH setup time
10
ns
t
OEH
OE HIGH hold time
10
ns
t
WP
WE pulse width
100
ns
t
WPH
WE High recovery
100
ns
t
DV
Data valid
1
μs
t
DS
Data setup
50
ns
t
DH
Data hold
0
ns
t
DW
Delay to next write
10
μs
t
BLC
Byte load cycle
0.2
100
μs
Address
t
AS
t
WC
t
AH
t
OES
t
DV
t
DS
t
DH
t
OEH
CE
WE
OE
Data In
Data Out
HIGH Z
Data Valid
t
CS
t
CH
t
WP
X28C512, X28C513
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