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參數(shù)資料
| 型號： | X28HC256PIZ-15 |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 Volt, Byte Alterable EEPROM |
| 中文描述： | 32K X 8 EEPROM 5V, 150 ns, PDIP28 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-011AB, DIP-28 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 294K |
| 代理商： | X28HC256PIZ-15 |
1
FN8108.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X28HC256
256K, 32K x 8 Bit
5 Volt, Byte Alterable EEPROM
FEATURES
Access time: 70ns
Simple byte and page write
—Single 5V supply
—No external high voltages or V
PP
control circuits
—Self-timed
—No erase before write
—No complex programming algorithms
—No overerase problem
Low power CMOS
—Active: 60mA
—Standby: 500μA
Software data protection
—Protects data against system level inadvertent
writes
High speed page write capability
Highly reliable Direct Write
cell
—Endurance: 1,000,000 cycles
—Data retention: 100 years
Early end of write detection
—DATA polling
—Toggle bit polling
Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X28HC256 is a second generation high perfor-
mance CMOS 32K x 8 EEPROM. It is fabricated with
Intersil’s proprietary, textured poly floating gate tech-
nology, providing a highly reliable 5 Volt only nonvola-
tile memory.
The X28HC256 supports a 128-byte page write opera-
tion, effectively providing a 24μs/byte write cycle, and
enabling the entire memory to be typically rewritten in
less than 0.8 seconds. The X28HC256 also features
DATA Polling and Toggle Bit Polling, two methods of
providing early end of write detection. The X28HC256
also supports the JEDEC standard Software Data Pro-
tection feature for protecting against inadvertent writes
during power-up and power-down.
Endurance for the X28HC256 is specified as a mini-
mum 1,000,000 write cycles per byte and an inherent
data retention of 100 years.
BLOCK DIAGRAM
X Buffers
Latches and
Decoder
I/O Buffers
and Latches
Y Buffers
Latches and
DECODER
Control
Logic and
Timing
256Kbit
EEPROM
Array
I/O
0
–I/O
7
Data Inputs/Outputs
CE
OE
V
CC
V
SS
A
0
–A
14
Address
Inputs
WE
Data Sheet
May 17, 2006
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X28HC256JIZ-12 | 5 Volt, Byte Alterable EEPROM |
| X28HC256JIZ-15 | 5 Volt, Byte Alterable EEPROM |
| X28HC256JZ-12 | 5 Volt, Byte Alterable EEPROM |
| X28HC256JZ-15 | 5 Volt, Byte Alterable EEPROM |
| X28HC256PIZ-12 | 5 Volt, Byte Alterable EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X28HC256PIZ-90 | 制造商:Intersil Corporation 功能描述:EEPROM PARALLEL 256KBIT 32KX8 5V 28PDIP - Rail/Tube |
| X28HC256PM-12 | 制造商:Intersil Corporation 功能描述:EEPROM PARALLEL 256KBIT 32KX8 5V 28PDIP - Bulk |
| X28HC256PM-15 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:5V, Byte Alterable EEPROM |
| X28HC256PM-70 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:5 Volt, Byte Alterable EEPROM |
| X28HC256PM-90 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:5 Volt, Byte Alterable EEPROM |
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