參數(shù)資料
型號(hào): X28C513JZ-15
廠商: INTERSIL CORP
元件分類: DRAM
英文描述: 5V, Byte Alterable EEPROM
中文描述: 64K X 8 EEPROM 5V, 150 ns, PQCC32
封裝: ROHS COMPLIANT, PLASTIC, MS-016AE, LCC-32
文件頁數(shù): 15/21頁
文件大?。?/td> 473K
代理商: X28C513JZ-15
15
FN8106.2
June 7, 2006
CE Controlled Write Cycle
Page Write Cycle
NOTES:
5. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch
data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
6. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the
CE or WE controlled write cycle timing.
Address
t
AS
t
OEH
t
WC
t
AH
t
OES
t
CS
t
DV
t
DS
t
DH
t
CH
CE
WE
OE
Data In
Data Out
HIGH Z
Data Valid
t
CW
t
WPH
WE
OE
Last Byte
Byte 0
Byte 1
Byte 2
Byte n
Byte n+1
Byte n+2
t
WP
t
WPH
t
BLC
t
WC
CE
Address*
(Note 6)
I/O
*For each successive write within the page write operation, A
7
-A
15
should be the same or
writes to an unknown address could occur.
(Note 5)
X28C512, X28C513
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