- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376437 > X28HC256JIZ-15 (INTERSIL CORP) 5 Volt, Byte Alterable EEPROM PDF資料下載
參數(shù)資料
| 型號： | X28HC256JIZ-15 |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 Volt, Byte Alterable EEPROM |
| 中文描述： | 32K X 8 EEPROM 5V, 150 ns, PQCC32 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-016AE, LCC-32 |
| 文件頁數(shù)： | 7/15頁 |
| 文件大小： | 294K |
| 代理商： | X28HC256JIZ-15 |
7
FN8108.1
May 17, 2006
THE TOGGLE BIT I/O
6
Figure 4. Toggle Bit Bus Sequence
Figure 5. Toggle Bit Software Flow
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to implement
DATA Polling. This can be especially helpful in an
array comprised of multiple X28HC256 memories that
is frequently updated. The timing diagram in Figure 4
illustrates the sequence of events on the bus. The
software flow diagram in Figure 5 illustrates a method
for polling the Toggle Bit.
HARDWARE DATA PROTECTION
The X28HC256 provides two hardware features that
protect nonvolatile data from inadvertent writes.
– Default V
CC
Sense—All write functions are inhibited
when V
CC
is 3.5V typically.
– Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
SOFTWARE DATA PROTECTION
The X28HC256 offers a software-controlled data pro-
tection feature. The X28HC256 is shipped from Intersil
with the software data protection NOT ENABLED; that
is, the device will be in the standard operating mode.
In this mode data should be protected during power-
up/down operations through the use of external cir-
cuits. The host would then have open read and write
access of the device once V
CC
was stable.
The X28HC256 can be automatically protected during
power-up and power-down (without the need for exter-
nal circuits) by employing the software data protection
feature. The internal software data protection circuit is
enabled after the first write operation, utilizing the soft-
ware algorithm. This circuit is nonvolatile, and will
remain set for the life of the device unless the reset
command is issued.
Once the software protection is enabled, the X28HC256 is
also protected from inadvertent and accidental writes in
the powered-up state. That is, the software algorithm must
be issued prior to writing additional data to the device.
CE
OE
WE
X28C512/513
Ready
Last
Write
I/O
6
HIGH Z
*
*
V
OH
V
OL
* I/O
6
Beginning and ending state of I/O
6
will vary.
Compare
ok
X28C256
No
Yes
Compare
Accum with
Addr n
Load Accum
From Addr n
Last Write
Yes
X28HC256
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X28HC256JZ-12 | 5 Volt, Byte Alterable EEPROM |
| X28HC256JZ-15 | 5 Volt, Byte Alterable EEPROM |
| X28HC256PIZ-12 | 5 Volt, Byte Alterable EEPROM |
| X28HC256PZ-12 | 5 Volt, Byte Alterable EEPROM |
| X28HC256PZ-15 | 5 Volt, Byte Alterable EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X28HC256JIZ-15T1 | 功能描述:IC EEPROM 256KBIT 150NS 32PLCC RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:1M (64K x 16) 速度:150ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| X28HC256JIZ-90 | 制造商:Intersil Corporation 功能描述:EEPROM PARALLEL 256KBIT 32KX8 5V 32PLCC - Rail/Tube |
| X28HC256JIZ-90T1 | 制造商:Intersil Corporation 功能描述:32K X 8 EEPROM,CMOS,HIGHSPEED,32LD PLCC,IND.,90NS, PB FREE,T - Tape and Reel |
| X28HC256JM-12 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:5 Volt, Byte Alterable EEPROM |
| X28HC256JM-15 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:5V, Byte Alterable EEPROM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。