參數(shù)資料
型號(hào): X28HC256PIZ-15
廠(chǎng)商: INTERSIL CORP
元件分類(lèi): DRAM
英文描述: 5 Volt, Byte Alterable EEPROM
中文描述: 32K X 8 EEPROM 5V, 150 ns, PDIP28
封裝: ROHS COMPLIANT, PLASTIC, MS-011AB, DIP-28
文件頁(yè)數(shù): 4/15頁(yè)
文件大小: 294K
代理商: X28HC256PIZ-15
4
FN8108.1
May 17, 2006
PIN CONFIGURATION
PIN DESCRIPTIONS
Addresses (A
0
-A
14
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all
read/write operations. When CE is HIGH, power con-
sumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buff-
ers, and is used to initiate read operations.
Data In/Data Out (I/O
0
-I/O
7
)
Data is written to or read from the X28HC256 through
the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to
the X28HC256.
PIN NAMES
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
X28HC256
PLASTIC DIP
CERDIP
FLAT PLASTIC
SOIC
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
I/O
6
4 3
2 1 32 31 30
14 15 16 17 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
LCC
PLCC
A
7
I
1
I
2
V
S
I
3
I
4
I
5
(Top View)
A
1
A
1
N
V
C
W
A
1
N
X28HC256
11
I/O
0
10
A
0
14
V
SS
9
A
1
8
A
2
7
A
3
6
A
4
5
A
5
2
A
12
28
V
CC
12
I/O
1
13
I/O
2
15
I/O
3
4
A
6
3
A
7
1
16
I/O
4
20
CE
22
OE
24
A
9
17
I/O
5
27
WE
19
I/O
7
21
A
10
23
A
11
25
A
8
18
I/O
6
26
A
13
(Bottom View)
PGA
A
14
X28HC256
Symbol
Description
A
0
-A
14
I/O
0
-I/O
7
WE
CE
OE
V
CC
V
SS
NC
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
X28HC256
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