參數(shù)資料
型號： X28HC64SZ-70
廠商： INTERSIL CORP
元件分類： DRAM
英文描述： 5 Volt, Byte Alterable EEPROM
中文描述： 8K X 8 EEPROM 5V, 70 ns, PDSO28
封裝： 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-013AE, SOIC-28
文件頁數(shù)： 1/17頁
文件大?。?/td> 265K
代理商： X28HC64SZ-70
1
FN8109.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X28HC64
64K, 8K x 8 Bit
5 Volt, Byte Alterable EEPROM
FEATURES
70ns access time
Simple byte and page write
—Single 5V supply
—No external high voltages or V
PP
control circuits
—Self-timed
—No erase before write
—No complex programming algorithms
—No overerase problem
Low power CMOS
—40mA active current max.
—200μA standby current max.
Fast write cycle times
—64-byte page write operation
—Byte or page write cycle: 2ms typical
—Complete memory rewrite: 0.25 sec. typical
—Effective byte write cycle time: 32μs typical
Software data protection
End of write detection
—DATA polling
—Toggle bit
High reliability
—Endurance: 1 million cycles
—Data retention: 100 years
JEDEC approved byte-wide pin out
Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X28HC64 is an 8K x 8 EEPROM, fabricated with
Intersil’s proprietary, high performance, floating gate
CMOS technology. Like all Intersil programmable non-
volatile memories, the X28HC64 is a 5V only device. It
features the JEDEC approved pinout for byte-wide
memories, compatible with industry standard RAMs.
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32μs/byte write cycle, and
enabling the entire memory to be typically written in 0.25
seconds. The X28HC64 also features DATA Polling and
Toggle Bit Polling, two methods providing early end of
write detection. In addition, the X28HC64 includes a
user-optional software data protection mode that further
enhances Intersil’s hardware write protect capability.
Intersil EEPROMs are designed and tested for appli-
cations requiring extended endurance. Inherent data
retention is greater than 100 years.
PIN CONFIGURATIONS
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
NC
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
X28HC64
Plastic DIP
Flat Pack
CERDIP
SOIC
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
7
I/O
6
4 3
2 1 32 31 30
14 15 16 17 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
LCC
PLCC
A
7
I
1
I
2
V
S
I
3
I
4
I
5
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A3
A4
A5
A6
A7
A12
NC
NC
VCC
WE
NC
A8
A9
A11
OE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A2
A1
A0
I/O0
I/O1
I/O2
NC
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
A
1
N
V
C
W
N
X28HC64
X28HC64
11
I/O
0
10
A
0
14
V
SS
9
A
1
8
A
2
7
A
3
6
A
4
5
A
5
2
A
12
28
V
CC
12
I/O
1
13
I/O
2
15
I/O
3
4
A
6
3
A
7
1
16
I/O
4
20
CE
22
OE
24
A
9
17
I/O
5
27
WE
19
I/O
7
21
A
10
23
A
11
25
A
8
18
I/O
6
26
NC
(BOTTOM
VIEW)
PGA
NC
X28HC64
TSOP
N
N
Bottom View
Data Sheet
June 7, 2006
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