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參數(shù)資料
| 型號： | X28HT010W |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5V, Byte Alterable EEPROM |
| 中文描述： | 128K X 8 EEPROM 5V, 200 ns, UUC |
| 封裝： | WAFER |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 444K |
| 代理商： | X28HT010W |
1
FN8105.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X28C010, X28HT010
5V, Byte Alterable EEPROM
The Intersil X28C010/X28HT010 is a 128K x 8 EEPROM,
fabricated with Intersil's proprietary, high performance,
floating gate CMOS technology. Like all Intersil
programmable non-volatile memories, the
X28C010/X28HT010 is a 5V only device. The
X28C010/X28HT010 features the JEDEC approved pin out
for byte-wide memories, compatible with industry standard
EEPROMs.
The X28C010/X28HT010 supports a 256-byte page write
operation, effectively providing a 19μs/byte write cycle and
enabling the entire memory to be typically written in less
than 2.5 seconds. The X28C010/X28HT010 also features
DATA Polling and Toggle Bit Polling, system software
support schemes used to indicate the early completion of a
write cycle. In addition, the X28C010/X28HT010 supports
Software Data Protection option.
Intersil EEPROMs are designed and tested for applications
requiring extended endurance. Data retention is specified to
be greater than 100 years.
Features
Access time: 120ns
Simple byte and page write
- Single 5V supply
- No external high voltages or V
PP
control
circuits
- Self-timed
No erase before write
No complex programming algorithms
No overerase problem
Low power CMOS
- Active: 50mA
- Standby: 500μA
Software data protection
- Protects data against system level inadvertent writes
High speed page write capability
Highly reliable Direct Write
cell
- Endurance: 100,000 write cycles
- Data retention: 100 years
Early end of write detection
- DATA polling
- Toggle bit polling
X28HT010 is fuly functional @ +175°C
Pinouts
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
X28C010
CERDIP
Flat Pack
SOIC (R)
PGA
X28C010
(Bottom View)
14
A0
16
I/O1
18
VSS
11
A3
9
A5
7
A7
15
I/O0
17
I/O2
19
I/O3
5
A15
2
NC
36
VCC
20
I/O4
21
I/O5
34
NC
23
I/O7
25
A10
27
A11
29
A8
22
I/O6
32
NC
24
CE
26
OE
28
A9
30
A13
13
A1
12
A2
10
A4
8
A6
4
A16
3
NC
1
NC
35
WE
33
NC
31
A14
6
A12
X28C010
(Top View)
A6
A5
A4
A3
A2
A1
A0
I/O0
A13
A8
A9
A11
OE
A10
CE
I/O7
A14
I
I2
V
I3
I
I5
I6
A
A1
A
N
VC
W
N
A7
30
EXTENDED LCC
22
21
23
24
25
26
27
28
29
6
7
5
8
9
10
11
12
13
2
32
4 3
31
1
15
17
16
18 1920
14
Data Sheet
February 12, 2007
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