參數(shù)資料
型號(hào)： X40431S14IZ-B
廠商： INTERSIL CORP
元件分類： 電源管理
英文描述： Triple Voltage Monitor with Integrated CPU Supervisor
中文描述： 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14
封裝： 0.150 INCH, ROHS COMPLIANT, SOIC-14
文件頁(yè)數(shù)： 26/26頁(yè)
文件大?。?/td> 399K
代理商： X40431S14IZ-B
26
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8251.1
May 24, 2006
X40430, X40431, X40434, X40435
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA
E1
D
N
1
2
3
-B-
0.10(0.004)
C A
M
B S
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E
0.25(0.010)
B
M
M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M
-
1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.041
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.195
0.199
4.95
5.05
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
N
α
14
14
7
0
o
8
o
0
o
8
o
-
Rev. 2 4/06
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
X40431S14IZ-BT1 制造商:Intersil Corporation 功能描述:PROCESSOR SUPERVISOR 4.4V/2.6V/1.7V 3000UA 14SOIC - Tape and Reel 制造商:Intersil Corporation 功能描述:Supervisory Circuits TRPL SUP 4K II2S LO I VT1 4 4 VT2 2 6 VT
X40431S14Z-A 制造商:Intersil Corporation 功能描述:PROCESSOR SUPERVISOR 4.6V/2.9V/1.7V 3000UA 14SOIC - Rail/Tube 制造商:Intersil Corporation 功能描述:Supervisory Circuits TRPL SUP 4K II2S LO VT1 4 6 VT2 2 9 VT3
X40431S14Z-AT1 制造商:Intersil Corporation 功能描述:PROCESSOR SUPERVISOR 4.6V/2.9V/1.7V 3000UA 14SOIC - Tape and Reel 制造商:Intersil Corporation 功能描述:Supervisory Circuits TRPL SUP 4K II2S LO VT1 4 6 VT2 2 9 VT3
X40431S14Z-B 制造商:Intersil Corporation 功能描述:PROCESSOR SUPERVISOR 4.4V/2.6V/1.7V 3000UA 14SOIC - Rail/Tube 制造商:Intersil Corporation 功能描述:Supervisory Circuits TRPL SUP 4K II2S LO VT1 4 4 VT2 2 6 VT3
X40431S14Z-BT1 制造商:Intersil Corporation 功能描述:PROCESSOR SUPERVISOR 4.4V/2.6V/1.7V 3000UA 14SOIC - Tape and Reel 制造商:Intersil Corporation 功能描述:Supervisory Circuits TRPL SUP 4K II2S LO VT1 4 4 VT2 2 6 VT3
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