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參數(shù)資料
| 型號： | X40435V14IZ-A |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Triple Voltage Monitor with Integrated CPU Supervisor |
| 中文描述： | 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14 |
| 封裝： | 4.40 MM, ROHS COMPLIANT, PLASTIC, MO-153AC, TSSOP-14 |
| 文件頁數(shù)： | 13/26頁 |
| 文件大?。?/td> | 399K |
| 代理商： | X40435V14IZ-A |
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13
FN8251.1
May 24, 2006
Serial Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. See Figure 9.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
Serial Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives
the master access to any one of the words in the
array. After receipt of the Word Address Byte, the
device responds with an acknowledge, and awaits the
next eight bits of data. After receiving the 8 bits of the
Data Byte, the device again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the
device begins the internal write cycle to the nonvolatile
memory. During this internal write cycle, the device
inputs are disabled, so the device will not respond to any
requests from the master. The SDA output is at high
impedance. See Figure 10.
A write to a protected block of memory will suppress
the acknowledge bit.
Figure 9. Acknowledge Response From Receiver
Figure 10. Byte Write Sequence
Data Output from
Transmitter
Data Output
from Receiver
8
1
9
Start
Acknowledge
SCL from
Master
S
t
a
r
t
S
t
o
p
Slave
Address
Byte
Address
Data
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
X40430, X40431, X40434, X40435
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X40435V14IZ-B | Triple Voltage Monitor with Integrated CPU Supervisor |
| X40435V14Z-A | Triple Voltage Monitor with Integrated CPU Supervisor |
| X40435V14Z-B | Triple Voltage Monitor with Integrated CPU Supervisor |
| X40430S14IZ-A | Triple Voltage Monitor with Integrated CPU Supervisor |
| X40430S14IZ-B | Triple Voltage Monitor with Integrated CPU Supervisor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X40435V14IZ-B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitor with Integrated CPU Supervisor |
| X40435V14Z-A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitor with Integrated CPU Supervisor |
| X40435V14Z-B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitor with Integrated CPU Supervisor |
| X4043M8 | 功能描述:IC CPU SUPERV 4K EE RST LO 8MSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復(fù)位:低有效 復(fù)位超時:標(biāo)準(zhǔn)傳輸延遲為 60 µs 電壓 - 閥值:3V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SC-74A，SOT-753 供應(yīng)商設(shè)備封裝:SOT-23-5 包裝:Digi-Reel® 其它名稱:LM8364BALMF30DKR |
| X4043M8-1.8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
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