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| 型號(hào)： | X40435V14IZ-A |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Triple Voltage Monitor with Integrated CPU Supervisor |
| 中文描述： | 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14 |
| 封裝： | 4.40 MM, ROHS COMPLIANT, PLASTIC, MO-153AC, TSSOP-14 |
| 文件頁(yè)數(shù)： | 9/26頁(yè) |
| 文件大小： | 399K |
| 代理商： | X40435V14IZ-A |
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9
FN8251.1
May 24, 2006
Setting a V
TRIPx
Voltage (x = 1, 2, 3)
There are two procedures used to set the threshold
voltages (V
TRIPx
), depending if the threshold voltage
to be stored is higher or lower than the present value.
For example, if the present V
TRIPx
is 2.9 V and the
new V
TRIPx
is 3.2 V, the new voltage can be stored
directly into the V
TRIPx
cell. If however, the new setting
is to be lower than the present setting, then it is neces-
sary to “reset” the V
TRIPx
voltage before setting the
new value.
Setting a Higher V
TRIPx
Voltage (x = 1, 2, 3)
To set a V
TRIPx
threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired V
TRIPx
threshold voltage to the corre-
sponding input pin Vcc(V1MON), V2MON or V3MON.
Then, a programming voltage (Vp) must be applied to the
WDO pin before a START condition is set up on SDA.
Next, issue on the SDA pin the Slave Address A0h, fol-
lowed by the Byte Address 01h for V
TRIP1
, 09h for
V
TRIP2
, and 0Dh for V
TRIP3
, and a 00h Data Byte in order
to program V
TRIPx
. The STOP bit following a valid write
operation initiates the programming sequence. Pin WDO
must then be brought LOW to complete the operation. To
check if the V
TRIPX
has been set, set VXMON to a value
slightly greater than V
TRIPX
(that was previously set).
Slowly ramp down VXMON and observe when the corre-
sponding outputs (LOWLINE, V2FAIL and V3FAIL)
switch. The voltage at which this occurs is the V
TRIPX
(actual).
C
ASE
A
Now if the desired V
TRIPX
is greater than the V
TRIPX
(actual), then add the difference between V
TRIPX
(desired) – V
TRIPX
(actual) to the original V
TRIPX
desired. This is your new V
TRIPX
that should be
applied to VXMON and the whole sequence should be
repeated again (see Figure 5).
C
ASE
B
Now if the V
TRIPX
(actual), is higher than the V
TRIPX
(desired), perform the reset sequence as described in
the next section. The new V
TRIPX
voltage to be applied
to VXMON will now be: V
TRIPX
(desired) – (V
TRIPX
(actual) – V
TRIPX
(desired)).
Note:
This operation does not corrupt the memory array.
Setting a Lower V
TRIPx
Voltage (x = 1, 2, 3)
In order to set V
TRIPx
to a lower voltage than the
present value, then V
TRIPx
must first be “reset” accord-
ing to the procedure described below. Once V
TRIPx
has been “reset”, then V
TRIPx
can be set to the desired
voltage using the procedure described in “Setting a
Higher V
TRIPx
Voltage”.
Resetting the V
TRIPx
Voltage
To reset a V
TRIPx
voltage, apply the programming volt-
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V
TRIP1
, 0Bh for V
TRIP2
, and 0Fh for V
TRIP3
, followed
by 00h for the Data Byte in order to reset V
TRIPx
. The
STOP bit following a valid write operation initiates the
programming sequence. Pin WDO must then be
brought LOW to complete the operation.
After being reset, the value of V
TRIPx
becomes a nomi-
nal value of 1.7V or lesser.
Notes: 1. This operation does not corrupt the memory array.
2. Set V
CC
1.5(V2MON or V3MON), when setting
V
TRIP2
or V
TRIP3
respectively.
CONTROL REGISTER
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is removed.
The Control Register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte write
operation directly to the address of the register and only
one data byte is allowed for each register write opera-
tion. Prior to writing to the Control Register, the WEL
and RWEL bits must be set using a two step process,
with the whole sequence requiring 3 steps. See "Writing
to the Control Registers" on page 11.
The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, and BP. The X40430,
X40431, X40434, X40435 will not acknowledge any
data bytes written after the first byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address 1FFh,
using the special preamble. Only one byte is read by
each register read operation. The master should
supply a stop condition to be consistent with the bus
protocol.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
7
6
5
4
3
2
1
0
PUP1 WD1
WD0
BP
0
RWEL WEL PUP0
X40430, X40431, X40434, X40435
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X40435V14IZ-B | Triple Voltage Monitor with Integrated CPU Supervisor |
| X40435V14Z-A | Triple Voltage Monitor with Integrated CPU Supervisor |
| X40435V14Z-B | Triple Voltage Monitor with Integrated CPU Supervisor |
| X40430S14IZ-A | Triple Voltage Monitor with Integrated CPU Supervisor |
| X40430S14IZ-B | Triple Voltage Monitor with Integrated CPU Supervisor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X40435V14IZ-B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitor with Integrated CPU Supervisor |
| X40435V14Z-A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitor with Integrated CPU Supervisor |
| X40435V14Z-B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitor with Integrated CPU Supervisor |
| X4043M8 | 功能描述:IC CPU SUPERV 4K EE RST LO 8MSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:開(kāi)路漏極或開(kāi)路集電極 復(fù)位:低有效 復(fù)位超時(shí):標(biāo)準(zhǔn)傳輸延遲為 60 µs 電壓 - 閥值:3V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SC-74A，SOT-753 供應(yīng)商設(shè)備封裝:SOT-23-5 包裝:Digi-Reel® 其它名稱:LM8364BALMF30DKR |
| X4043M8-1.8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
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