參數(shù)資料
型號: X4045P-2.7A
廠商: INTERSIL CORP
元件分類: 電源管理
英文描述: RTC Module With CPU Supervisor
中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8
封裝: PLASTIC, DIP-8
文件頁數(shù): 15/25頁
文件大?。?/td> 144K
代理商: X4045P-2.7A
X4043/45
Characteristics subject to change without notice.
15 of 25
REV 1.1.17 9/14/01
www.xicor.com
CAPACITANCE
(T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V)
Notes:
(4) This parameter is periodically sampled and not 100% tested.
Symbol
C
OUT
(4)
C
IN
(4)
Parameter
Max.
8
6
Unit
pF
pF
Test Conditions
V
OUT
= 0V
V
IN
= 0V
Output capacitance (SDA, RESET/RESET)
Input capacitance (SCL, WP)
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
5V
4.6K
RESET
100pF
SDA
1533
100pF
5V
For V
OL
= 0.4V
and I
OL
= 3 mA
Input pulse levels
Input rise and fall times
Input and output timing levels
Output load
0.1 V
CC
to 0.9 V
CC
10ns
0.5 V
CC
Standard output load
A.C. CHARACTERISTICS
(Over recommended operating conditions, unless otherwise specified)
Notes:
(5) Typical values are for T
A
= 25°C and V
CC
= 5.0V
(6) Cb = total capacitance of one bus line in pF.
Symbol
f
SCL
t
IN
t
AA
t
BUF
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
DH
t
R
t
F
t
SU:WP
t
HD:WP
Cb
Parameter
100kHz
Min.
0
n/a
0.1
4.7
4.7
4.0
4.7
4.0
250
5.0
0.6
50
400kHz
Min.
0
50
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 + .1Cb
(6)
20 + .1Cb
(6)
0.6
0
Unit
kHz
ns
μs
μs
μs
μs
μs
μs
ns
μs
μs
ns
ns
ns
μ
s
μ
s
pF
Max.
100
n/a
0.9
Max.
400
SCL clock frequency
Pulse width suppression time at inputs
SCL LOW to SDA data out valid
Time the bus free before start of new transmission
Clock LOW time
Clock HIGH time
Start condition setup time
Start condition hold time
Data in setup time
Data in hold time
Stop condition setup time
Data output hold time
SDA and SCL rise time
SDA and SCL fall time
WP setup time
WP hold time
Capacitive load for each bus line
0.9
1000
300
300
300
0.4
0
400
400
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