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參數(shù)資料
| 型號： | X4045S8IZ-2.7A |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | ROHS COMPLIANT, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 10/25頁 |
| 文件大小： | 144K |
| 代理商： | X4045S8IZ-2.7A |
X4043/45
Characteristics subject to change without notice.
10 of 25
REV 1.1.17 9/14/01
www.xicor.com
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page. This means that the
master can write 16 bytes to the page starting at any
location on that page. If the master begins writing at
location 10, and loads 12 bytes, then the first 5 bytes
are written to locations 10 through 15, and the last 7
bytes are written to locations 0 through 6. Afterwards,
the address counter would point to location 7 of the
page that was just written. If the master supplies more
than 16 bytes of data, then new data over-writes the
previous data, one byte at a time.
Figure 11. Page Write Operation
Figure 12. Writing 12-bytes to a 16-byte page starting at location 10
S
t
a
r
t
S
t
o
p
Slave
Address
Byte
Address
Data
(n)
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
Data
(1)
A
C
K
(1
≤
n
≤
16)
A
C
K
Address
n-1
Address
10
5 Bytes
7 Bytes
Address
= 6
Address Pointer
Ends Here
Addr = 7
The master terminates the data byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 11 for the address, acknowl-
edge, and data transfer sequence.
Stops and Write Modes
Stop conditions (that terminate write operations) must
be sent by the master after sending at least 1 full data
byte, plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full data
byte plus its associated ACK is sent, then the device
will reset itself without performing the write. The con-
tents of the array will not be effected.
Figure 10. Byte Write Sequence
.
S
t
a
r
t
S
t
o
p
Slave
Address
Byte
Address
Data
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
0
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