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參數(shù)資料
| 型號： | X4045S8IZ-2.7A |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | ROHS COMPLIANT, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 12/25頁 |
| 文件大小： | 144K |
| 代理商： | X4045S8IZ-2.7A |
X4043/45
Characteristics subject to change without notice.
12 of 25
REV 1.1.17 9/14/01
www.xicor.com
Figure 15. Random Address Read Sequence
0
Slave
Address
Byte
Address
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
1
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
There is a similar operation, called “Set Current
Address” where the device does no operation, but
enters a new address into the address counter if a stop
is issued instead of the second start shown in Figure
14. The device goes into standby mode after the stop
and all bus activity will be ignored until a start is
detected. The next current address read operation
reads from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first data
byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicating
it requires additional data. The device continues to out-
put data for each acknowledge received. The master
terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments
through all page and column addresses, allowing the
entire memory contents to be serially read during one
operation. At the end of the address space the counter
“rolls over” to address 0000
H
and the device continues
to output data for each acknowledge received. Refer to
Figure 16 for the acknowledge and data transfer
sequence.
Figure 16. Sequential Read Sequence
Data
(2)
S
t
o
p
Slave
Address
Data
(n)
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
1
Data
(n-1)
(n is any integer greater than 1)
Data
(1)
A
C
K
A
C
K
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
slave address byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the word address bytes. After acknowledging receipts
of the word address bytes, the master immediately
issues another start condition and the slave address
byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 15 for the address,
acknowledge, and data transfer sequence.
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