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參數(shù)資料
| 型號： | X5323V14I-2.7T1 |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14 |
| 封裝： | PLASTIC, TSSOP-14 |
| 文件頁數(shù)： | 20/21頁 |
| 文件大?。?/td> | 200K |
| 代理商： | X5323V14I-2.7T1 |
X5323/X5325
Characteristics subject to change without notice.
8 of 21
REV 1.1.2 11/13/01
www.xicor.com
For the page write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation will
not be completed (Figure 4).
To write to the status register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits
0 and 1 must be “0”.
While the write is in progress following a status register
or EEPROM Sequence, the status register may be
read to check the WIP bit. During this time the WIP bit
will be high.
OPERATIONAL NOTES
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The write enable latch is reset.
– The ag bit is reset.
– Reset signal is active for tPURST.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A WREN instruction must be issued to set the write
enable latch.
–CS must come HIGH at the proper clock count in
order to start a nonvolatile write cycle.
Figure 6. Read Status Register Sequence
Figure 7. Write Enable Latch Sequence
0123456789
10
11 12 13 14
76543210
Data Out
CS
SCK
SI
SO
MSB
High Impedance
Instruction
01234567
CS
SI
SCK
High Impedance
SO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X5328V14I | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO14 |
| XAVAC25M/FS.0 | 25-25 CONTACT(S), PANEL MOUNT, MALE-FEMALE, RECTANGULAR ADAPTER |
| XAVAC25M/FS.5 | 25-25 CONTACT(S), PANEL MOUNT, MALE-FEMALE, RECTANGULAR ADAPTER |
| XAVAC25M/MD.0 | 25-25 CONTACT(S), PANEL MOUNT, MALE-MALE, RECTANGULAR ADAPTER |
| XAVAC25M/MD.5 | 25-25 CONTACT(S), PANEL MOUNT, MALE-MALE, RECTANGULAR ADAPTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X5323V14I-4.5A | 功能描述:IC SUPERVISOR CPU 32K EE 14TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:推挽式，圖騰柱 復(fù)位:低有效 復(fù)位超時:最小 145 ms 電壓 - 閥值:2.64V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:16-TQFN-EP（4x4） 包裝:帶卷 (TR) |
| X5323V14IT1 | 功能描述:IC SUPERVISOR CPU 32K EE 14TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:簡單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:推挽式，圖騰柱 復(fù)位:低有效 復(fù)位超時:最小 145 ms 電壓 - 閥值:2.64V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:16-TQFN-EP（4x4） 包裝:帶卷 (TR) |
| X5323V14IZ | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CPU Supervisor with 32Kb SPI EEPROM |
| X5323V14IZ-2.7 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CPU Supervisor with 32Kb SPI EEPROM |
| X5323V14IZ-2.7A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CPU Supervisor with 32Kb SPI EEPROM |
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