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參數(shù)資料
| 型號(hào)： | X5643(中文) |
| 元件分類： | CPU監(jiān)測(cè) |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 時(shí)鐘模塊CPU監(jiān)控 |
| 文件頁數(shù)： | 2/23頁 |
| 文件大?。?/td> | 114K |
| 代理商： | X5643(中文) |
X5643/X5645
2
PIN DESCRIPTION
PIN CONFIGURATION
PIN
(SOIC/PDIP)
PIN
TSSOP
Name
Function
1
1
CS/WDI
Chip Select Input.
is at a high impedance state. Unless a nonvolatile write cycle is underway,
the device will be in the standby power mode. CS LOW enables the device,
placing it in the active power mode. Prior to the start of any operation after
power up, a HIGH to LOW transition on CS is required.
Watchdog Input.
A HIGH to LOW transition on the WDI pin restarts the
Watchdog timer. The absence of a HIGH to LOW transition within the
watchdog time-out period results in RESET/RESET going active.
Serial Output.
SO is a push/pull serial data output pin. A read cycle shifts data
out on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input.
SI is a serial data input pin. Input all opcodes, byte addresses,
and memory data on this pin. The rising edge of the serial clock (SCK) latches
the input data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and
output. The rising edge of SCK latches in the opcode, address, or data bits
present on the SI pin. The falling edge of SCK changes the data output on the
SO pin.
Write Protect.
The WP pin works in conjunction with a nonvolatile WPEN
bit to “l(fā)ock” the setting of the Watchdog Timer control and the memory write
protect bits.
CS HIGH, deselects the device and the SO output pin
2
2
SO
5
8
SI
6
9
SCK
3
6
WP
4
7
V
SS
Ground
8
14
V
CC
Supply Voltage
Reset Output
which goes active whenever Vcc falls below the minimum Vcc sense level.
It will remain active until Vcc rises above the minimum Vcc sense level for
200ms. RESET/RESET goes active if the Watchdog Timer is enabled and
CS remains either HIGH or LOW longer than the selectable Watchdog time-
out period. A falling edge of CS will reset the Watchdog Timer. RESET/RE-
SET goes active on power up at about 1V and remains active for 200ms af-
ter the power supply stabilizes.
No internal connections
7
13
RESET/
RESET
.
RESET/RESET is an active LOW/HIGH, open drain output
3-5,10-12
NC
8-LEAD PDIP
CS/WDI
WP
VSS
SO
1
2
3
4
RESET/RESET
SCK
SI
8
7
6
5
VCC
14-LEAD SOIC
SO
WP
VSS
NC
1
2
3
4
5
6
7
RESET/RESET
SCK
SI
NC
14
13
12
11
10
9
8
NC
VCC
VCC
NC
X5643/45
CS/WDI
X5643/45
CS/WDI
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| X5643S14-1.8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM with Supervisory Features |
| X5643S14-2.7 | 功能描述:IC CPU SUPRV 64K EE RST LO SO14 RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:開路漏極或開路集電極 復(fù)位:低有效 復(fù)位超時(shí):標(biāo)準(zhǔn)傳輸延遲為 60 µs 電壓 - 閥值:3V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:SC-74A，SOT-753 供應(yīng)商設(shè)備封裝:SOT-23-5 包裝:Digi-Reel® 其它名稱:LM8364BALMF30DKR |
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