參數(shù)資料
型號(hào)： X5643(中文)
元件分類： CPU監(jiān)測(cè)
英文描述： RTC Module With CPU Supervisor
中文描述： 時(shí)鐘模塊CPU監(jiān)控
文件頁(yè)數(shù)： 7/23頁(yè)
文件大小： 114K
代理商： X5643(中文)
X5643/X5645
7
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the Status Register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the Status Register.
When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally. Setting
the WPEN bit in the Status Register to “0” blocks the WP
pin function, allowing writes to the Status Register when
WP is HIGH or LOW. Setting the WPEN bit to “1” while
the WP pin is LOW activates the Programmable ROM
mode, thus requiring a change in the WP pin prior to sub-
sequent Status Register changes. This allows manufac-
turing to install the device in a system with WP pin
grounded and still be able to program the Status Regis-
ter. Manufacturing can then load Configuration data,
manufacturing time and other parameters into the
EEPROM, then set the portion of memory to be pro-
tected by setting the Block Lock bits, and finally set the
“OTP mode” by setting the WPEN bit. Data changes now
require a hardware change.
Read Sequence
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address are
sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored in
memory at the next address can be read sequentially by
continuing to provide clock pulses. The address is auto-
matically incremented to the next higher address after
each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
address $0000 allowing the read cycle to be continued
indefinitely. The read operation is terminated by taking
CS high. Refer to the Read EEPROM Array Sequence
(Figure 1).
To read the Status Register, the CS line is first pulled low
to select the device followed by the 8-bit RDSR instruc-
tion. After the RDSR opcode is sent, the contents of the
Status Register are shifted out on the SO line. Refer to
the Read Status Register Sequence (Figure 2).
Write Sequence
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the Write
Operation without taking CS HIGH after issuing the
WREN instruction, the Write Operation will be ignored.
To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16 bit
address and then the data to be written. Any unused
address bits are specified to be “0’s”. The WRITE opera-
tion minimally takes 32 clocks. CS must go low and
remain low for the duration of the operation. If the
address counter reaches the end of a page and the clock
continues, the counter will roll back to the first address of
the page and overwrite any data that may have been pre-
viously written.
For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
the last data byte to be written is clocked in. If it is brought
HIGH at any other time, the write operation will not be
completed (Figure 4).
To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits 0
and 1 must be “0” .
While the write is in progress following a Status Register
or EEPROM Sequence, the Status Register may be read
to check the WIP bit. During this time the WIP bit will be
high.
OPERATIONAL NOTES
The device powers-up in the following state:
The device is in the low power standby state.
A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
SO pin is high impedance.
The Write Enable Latch is reset.
The Flag Bit is reset.
Reset Signal is active for t
PURST
.
Data Protection
The following circuitry has been included to prevent inad-
vertent writes:
A WREN instruction must be issued to set the Write
Enable Latch.
CS must come HIGH at the proper clock count in order
to start a nonvolatile write cycle.
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