參數(shù)資料
型號(hào): X76F101Y-3.0
元件分類(lèi): EEPROM
英文描述: EEPROM
中文描述: EEPROM的
文件頁(yè)數(shù): 9/17頁(yè)
文件大小: 93K
代理商: X76F101Y-3.0
X76F101
9
AC CHARACTERISTICS
(T
A
= -40C to +85C, V
CC
= +3.0V to +5.5V, unless otherwise specified.)
Notes:
1.
These Specs are not defined in the ISO 7816-3 Standard, since CS is not defined.
C
b
= total capacitance of one bus line in pF
t
AA
= 1.1μs Max below V
CC
= 3.0V.
2.
3.
RESET AC SPECIFICATIONS
Power Up Timing
Notes:
1.
Delays are measured from the time V
CC
is stable until the specified operation can be initiated. These parameters are periodically sampled
and not 100% tested.
Typical values are for T
A
= 25C and V
CC
= 5.0V
2.
Symbol
Parameter
Min
Max
Units
f
SCL
t
AA(3)
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
DH
t
NOL
t
RDV
t
CDV
t
DHZ
(1)
t
SR
(1)
t
RST
t
SU:RST
t
SU:CS
t
SU:CS
SCL Clock Frequency
SCL LOW to SDA Data Out Valid
Time the Bus Must Be Free Before a New Transmission Can Start
Start Condition Hold Time
Clock LOW Period
Clock HIGH Period
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
RST to SCL Non-Overlap
0
1
MHz
0.1
1.2
0.6
1.2
0.6
0.6
0
100
0.9
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
ns
μ
s
μ
s
ns
ns
ns
ns
ns
μ
s
ns
ns
ns
20+0.1XC
b(2)
20+0.1XC
b(2)
0.6
0.1
500
0
0
0
0
1.5
500
200
100
300
300
RST LOW to SDA Valid During Response to Reset
450
450
450
CLK LOW to SDA Valid During Response to Reset
Device Deselect to SDA high impedance
Device Select to RST active
RST High Time
RST Setup Time
CS
Setup Time
CS
Hold Time
Symbol
t
PUR(1)
t
PUW(1)
Parameter
Min.
Typ
(2)
Max.
1
5
Units
mS
mS
Time from Power Up to Read
Time from Power Up to Write
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