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參數(shù)資料
| 型號： | X84041VI2.7 |
| 英文描述： | Serial EEPROM |
| 中文描述： | 串行EEPROM |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 137K |
| 代理商： | X84041VI2.7 |
X84041
Characteristics subject to change without notice.
3 of 13
REV 1.0 6/29/00
www.xicor.com
Sequential Read
The byte address is automatically incremented to the
next higher address after each byte of data is read.
The data stored in the memory at the next address can
be read sequentially by continuing to issue read
cycles. When the highest address is reached ($1FF),
the address counter rolls over to address $000 and
reading may be continued indefinitely.
Reset Sequence
The reset sequence resets the X84041 and sets an
internal write enable latch. A reset sequence can be
sent at any time by performing a read/write “0”/read
sequence (see Figs. 1 and 2). This sequence breaks
the multiple read or write cycle sequences that are nor-
mally used when reading from or writing to the part.
This sequence can be used at any time to interrupt or
end a sequential read or page load. As soon as the
write “0” cycle is complete, the part is reset (unless a
nonvolatile write cycle is in progress). The second read
cycle in this sequence, and any further read cycles, will
read a HIGH on the l/O pin until a valid read sequence
is issued. The reset sequence must be issued at the
beginning of both read and write sequences to be sure
the X84041 initiates these operations properly.
Figure 1. Read Sequence
CE
OE
WE
I/O (IN)
"0"
RESET
Load Address
Read Data
X
X
X
X
X
X
X A8
A7 A6 A5 A4 A3 A2 A1 A0
I/O (OUT)
D2 D1 D0
D3
D4
D5
D6
D7
Write Sequence
A nonvolatile write sequence consists of sending a
reset sequence, a 16-bit address (the first 7 of which
are don’t cares), up to 8 bytes of data, and then a spe-
cial “start nonvolatile write cycle” command sequence.
The reset sequence is issued first (as described in the
Reset Sequence section) to set the internal write
enable latch. The address is written serially by issuing
16 separate write cycles (WE and CE LOW, OE HIGH)
to the part without any read cycles between the writes.
The address is sent serially, most significant bit first, on
the l/O pin. Up to eight bytes of data are written by
issuing either 8, 16, 24, 32, 40, 48, 56, or 64 separate
write cycles. Again, no read cycles are allowed
between writes. The nonvolatile write cycle is initiated
by issuing a special read/write “1”/read sequence. The
first read cycle ends the page load, then the write “1”
followed by a read starts the nonvolatile write cycle.
The X84041 recognizes 8-byte pages beginning at
addresses XXXXXX000. When sending data to the
part, attempts to exceed the upper address of the page
will result in the address counter “wrapping-around” to
the first address on the page, where data loading can
continue. For this reason, sending more than 64 con-
secutive data bits will result in overwriting previous
data. A nonvolatile write cycle will not start if a partial
or incomplete write sequence is issued. The internal
write enable latch is reset when the nonvolatile write
cycle is completed to prevent inadvertent writes. Note
that this sequence is fully static, with no special timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X84041VI | Micro Port Saver E2PROM |
| X84041PI-2.7 | Micro Port Saver E2PROM |
| X84041SI-2.7 | Micro Port Saver E2PROM |
| X84041SI-3 | Micro Port Saver E2PROM |
| X84041VI-2.7 | Micro Port Saver E2PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X84041VI-3 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Micro Port Saver E2PROM |
| X84128 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced MPS⑩ Micro Port Saver EEPROM with Block Lock⑩ Protection |
| X84128-1.8 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced MPS⑩ Micro Port Saver EEPROM with Block Lock⑩ Protection |
| X84128-2.5 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced MPS⑩ Micro Port Saver EEPROM with Block Lock⑩ Protection |
| X84128E | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced MPS⑩ Micro Port Saver EEPROM with Block Lock⑩ Protection |
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