tHIGH
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tLOW
tF
tSU:STO
tR
tBUF
SCL
SDA
(Data in)
tAA
tDH
SCL
SDA
SDAOUT (ACK)
SDAOUT
12
FN8163.2
August 30, 2006
TIMING DIAGRAMS
Figure 10. Input Bus Timing
Figure 11. Output Bus Timing
A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated)
Symbol
Parameter
Limits
Unit
Reference
Figure
Min.
Max.
fSCL
SCL clock frequency
0
100
kHz
10
tLOW
Clock LOW period
4700
ns
10
tHIGH
Clock HIGH period
4000
ns
10
tR
SCL and SDA rise time
1000
ns
10
tF
SCL and SDA fall time
300
ns
10
Ti
Noise suppression time constant (glitch filter)
100
ns
10
tSU:STA
Start condition setup time (for a repeated start condition)
4700
ns
10 & 12
tHD:STA
Start condition hold time
4000
ns
10 & 12
tSU:DAT
Data in setup time
250
ns
10
tHD:DAT
Data in hold time
0
ns
10
tAA
SCL LOW to SDA data out valid
300
3500
ns
11
tDH
Data out hold time
300
ns
11
tSU:STO
Stop condition setup time
4700
ns
10 & 12
tBUF
Bus free time prior to new transmission
4700
ns
10
tWR
Write cycle time (nonvolatile write operation)
10
ms
13
tSTPWV
Wiper response time from stop generation
1000
s
13
tCLWV
Wiper response from SCL LOW
500
s
6
X9221A